• Title/Summary/Keyword: Band drain

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RELEVANCE OF BAND DRAIN QUALITY TO EFFECTIVENESS OF GROUND IMPROVEMENT (밴드 드레인의 품질과 연약지반개량효과와의 관련)

  • 김상규
    • Proceedings of the Korean Geotechical Society Conference
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    • 1995.10a
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    • pp.1.3-20
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    • 1995
  • The use of band drains for ground improvement has been increased throughout the world during the past 15 years. Apart from other ground improvement techniques, the quality of band drains affects greatly the well resistance of drains, discharge capacity and clogginf tests for four drains selected are carried out and quality is examined.

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한국에서의 PBD공법의 현황 및 문제점과 발전방향

  • 김영남;권성진
    • Proceedings of the Korean Geotechical Society Conference
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    • 2001.10a
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    • pp.65-94
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    • 2001
  • The use of PBD(prefabricated band drain)far ground improvement is rapidly increased due to the merit of construction period and cost, environmental preservation compared with other vertical drain method, and the development of material. This paper presents the historical review, theoretical background, design procedure and method, and typical construction example for the PBD. Also, the direction of further technical development and study is recommended.

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Performance Enhancement of Hybrid Doherty Amplifier using Drain bias control (Drain 바이어스 제어를 이용한 Hybrid Doherty 증폭기의 성능개선)

  • Lee Suk-Hui;Lee Sang-Ho;Bang Sung-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.5 s.347
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    • pp.128-136
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    • 2006
  • In this paper, design and implement 50W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of ideal Doherty power amplifier is distinguishable; however bias control for implementation of Doherty(GDCHD) amplifier is difficult. To solve the problem, therefore, GDCHD(Gate and Drain Control Hybrid Doherty) power amplifier is embodied to drain bias adjustment circuit to Doherty power amplifier with gate bias adjustment circuit. Experiment result shows that $2.11{\sim}2.17\;GHz$, 3GPP operating frequency band, with 57.03 dB gain, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and -40.45 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GDCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than Doherty power amplifier.

Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

  • Lee, Min-Jin;Choi, Woo-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.287-294
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    • 2011
  • In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift. Based on the results, the characteristics of TFETs have been discussed in the tunneling-dominant and drift-dominant region.

Pulsed-Bias Pulsed-RF Passive Load-Pull Measurement of an X-Band GaN HEMT Bare-chip (X-대역 GaN HEMT Bare-Chip 펄스-전압 펄스-RF 수동 로드-풀 측정)

  • Shin, Suk-Woo;Kim, Hyoung-Jong;Choi, Gil-Wong;Choi, Jin-Joo;Lim, Byeong-Ok;Lee, Bok-Hyung
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.10 no.1
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    • pp.42-48
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    • 2011
  • In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

Reduction of Barrier Height between Ni-silicide and p+ source/drain for High Performance PMOSFET (고성능 PMOSFET을 위한 Ni-silicide와 p+ source/drain 사이의 barrier height 감소)

  • Kong, Sun-Kyu;Zhang, Ying-Ying;Park, Kee-Young;Li, Shi-Guang;Zhong, Zhun;Jung, Soon-Yen;Yim, Kyoung-Yean;Lee, Ga-Won;Wang, Jin-Suk;Lee, Hi-Deok
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.157-157
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    • 2008
  • As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

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Schottky barrier overlapping in short channel SB-MOSFETs (Short Channel SB-FETs의 Schottky 장벽 Overlapping)

  • Choi, Chang-Yong;Cho, Won-Ju;Chung, Hong-Bay;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.133-133
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    • 2008
  • Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

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Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

  • Vanitha, P.;Balamurugan, N.B.;Priya, G. Lakshmi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.585-593
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    • 2015
  • In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

The Design of Low Noise Downconverter for K-band Satellite Multipoint Distribution Service (K-band SMDS용 저잡음 하향변환기의 설계)

  • 정인기;이영철;김천석
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.6
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    • pp.1143-1150
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    • 2001
  • In this paper, we designed a downconverter for K-band satellite multipoint distribution service(SMDS). The designed downconverter consists of a low noise amplifiers, bandpass filter, stable local oscillator, drain mixer and If Amplifiers. Low noise amplifiers show 28㏈ gain and 1.5㏈ noise figure in the frequency range of 19.2㎓~20.2㎓, and a band pass filter has a -l㏈ insertion loss, and 18.25㎓ Stable local oscillator which is dielectric resonant oscillation, We obtained that the output power of the 18.25㎓ oscillation frequency is 0.5㏈m and the phase noise is the -84.67㏈c at 10KHz offset frequency. With the input RF signal the 19.2㎓~20.2㎓, conversion gain of the drain mixer shows 5㏈ at the Intermediate frequency range of 950MHz~1950MHz. We have proved that the designed downconverter satisfied the specification of a K-band satellite multipoint distribution service and it can be applied to the satellite internet receiver.

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Performance Enhancement of 3-way Doherty Power Amplifier using Gate and Drain bias control (Gate 및 Drain 바이어스 제어를 이용한 3-way Doherty 전력증폭기와 성능개선)

  • Lee, Kwang-Ho;Lee, Suk-Hui;Bang, Sung-Il
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.1
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    • pp.77-83
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    • 2011
  • In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.