• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.461-463
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• 1999

In this paper, we have systematically investigated the variation of electrical characteristics with back-gate bias of n-channel SOI MOSFET\\`s. When positive bias is applied back-gate surface is inverted and back channel current is increased. When negative bias is applied back-gate surface is accumulated but it does not affect to the electrical characteristics.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.178-180
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• 1993

The back bias effect on the breakdown voltage of SOI $p^+$-n diode is investigated. The breakdown voltage of the SOI $p^+$-n diode increases with the applied back bias. When the cathode electrode is used as a back bias, it is necessary to put the dielectric material between the Si-substrate and the bottom cathode electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.485-488
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• 1999

In this paper, the effects of back-gate bias on n-channel SOI MOSFETs has been systematically investigated. Back-gate surface is accumulated when negative bias is applied. It is found that the driving current ability of SOI MOSFETs is reduced because the threshold voltage and subthreshold slope are increased and transconductance is decreased due to the hole accumulation in Si body.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.

• ETRI Journal
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• v.32 no.3
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• pp.406-413
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• 2010

In order to guarantee the proper operation of a recessed channel array transistor (RCAT) pseudo SRAM, the back-bias voltage must be changed in response to changes in temperature. Due to cell drivability and leakage current, the obtainable back-bias range also changes with temperature. This paper presents a pseudo SRAM for mobile applications with an adaptive back-bias voltage generator with a negative temperature dependency (NTD) using an NTD VBB detector. The proposed scheme is implemented using the Samsung 100 nm RCAT pseudo SRAM process technology. Experimental results show that the proposed VBB generator has a negative temperature dependency of -0.85 $mV/^{\circ}C$, and its static current consumption is found to be only 0.83 ${\mu}A$@2.0 V.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.195-199
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• 2002

This paper describes the effect of substrate back bias of CMOS Inverter. When the substrate back bias applied in body, the MOS transistor threshold voltage increased and drain saturation current decreased. The back gate reverse bias or substrate bias has been widely utilized and the following advantage has suppressing subthreshold leakage, lowering parasitic junction capacitance, preventing latch up or parasitic bipolar transistor, etc. When the reverse voltage applied substrate, this paper stimulated the propagation delay time CMOS inverter.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.10
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• pp.869-875
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• 2016

In this paper, a novel scheme with which to mitigate a repeat-back jamming effect is proposed for the GPS L1 coarse/acquisition signal. The proposed scheme estimates the code tracking bias caused by repeat-back jamming signals using a Combined Pseudo-random noise signal. It then mitigates the repeat-back jamming effect by subtracting the estimated code timing on a normal correlation channel from the estimated value. Through a Monte-Carlo simulation, the proposed scheme can diminish the running average of code tracking bias to less than 10% of the bias using the conventional scheme.

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.875-878
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• 1999

In this paper, we measured and simulated the transconductance change of submicron LDD NMOSFETs due to back bias under various channel length, temperature and substrate doping conditions. As back bias is increased, the mobility will decrease and g$_{m}$ decreases according to a conventional model. But as the channel length is reduced, this phenomenon is inverted and g$_{m}$ increases in the submicron region. This can be explained by analyzing the electron quasi Fermi potential in the channel. And the empirical formulae which show the g$_{m}$ change were induced. These will be helpful to enhance the efficiency and precision of IC design.esign.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.