• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.1-9
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• 2010

We reported the methodology for the shear test which is one of the evaluation procedure for mechanical reliability of flip-chip package. The shear speed and the tip height are found to be two significant experimental parameters in the shear test. We investigated how these two parameters have an influence on the results, the shear strength and failure mode. In order to prove these experimental inconsistency, simulation using finite element analysis was also conducted to calculate the shear strength and to figure out the distribution of plastic energy inside of the solder ball. The shear strength decreased while the tip height increased or the shear speed decreased. A variation in shear strength due to inconsistent shear conditions made confusion on analyzing experimental results. As a result, it was strongly needed to standardize the shear test method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.9
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• pp.789-794
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• 2014

The FPGA is used to the high speed digital satellite communication on the Digital Signal Process Unit of the next generation GEO communication satellite. The high capacity FPGA has the high power dissipation and it is difficult to satisfy the derating requirement of temperature. This matter is the major factor to degrade the equipment life and reliability. The thermal control at the equipment level has been worked through thermal conduction in the space environment. The FPGA of CCGA or BGA package type was mounted on printed circuit board, but the PCB has low efficient to the thermal control. For the FPGA heat dissipation, the heat sink was applied between part lid and housing of equipment and the performance of heat sink was confirmed via thermal vacuum test under the condition of space qualification level. The FPGA of high power dissipation has been difficult to apply for space application, but FPGA with heat sink could be used to space application with the derating temperature margin.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.59-65
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• 2011

According to the trends of electronic package to be smaller, thinner and more integrative, Flip Chip Ball Grid Array (FCBGA) become more used for mobile phone. However, the flip chip necessarily generate the heat by the electrical resistance and generated heat is increased due to reduced distribution area of the heat in accordance with the miniaturization trend of the package. Thermal issues can result in problems of devices that are sensitive to temperature and stress. Then the heat can generate problems to the system. In this paper, in order to improve the thermal issues of FCBGA, thermal characteristics of FCBGA was analyzed qualitatively by using the general heat transfer module of Comsol 3.5a and In order to solve thermal issues, flip chip with new micro structure is proposed by the simulation. and also by comparing existing model and analyzing variables such as pitch, height of the pattern and shape of the heat spreader, the improvement of heat dissipation characteristics about 18% was confirmed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.481-486
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• 2010

ENIG (electroless Ni immersion gold) is one of surface finishing which has been most widely used in fine pitch SMT (surface mount technology) and BGA (ball grid array) packaging process. The reliability for package bondability is mainly affected by interfacial reaction between solder and surface finishing. Since the behavior of IMC (intermetallic compound), or the interfacial reaction between Ni and solder, affects to some product reliabilities such as solderability and bondability, understanding behavior of IMC should be important issue. Thus, we studied the properties of ENIG with P contents (9 wt% and 13 wt%), where the P contents is one of main factors in formation of IMC layer. The effect of P content was discussed using the results obtained from FE-SEM(field-emission scanning electron microscope), EPMA(electron probe micro analyzer), EDS(energy dispersive spectroscopy) and Dual-FIB(focused ion beam). Especially, we observed needle type irregular IMC layer with decreasing Ni contents under high P contents (13 wt%). Also, we found how IMC layer affects to bondability with forming continuous Kirkendall voids and thick P-rich layer.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Korean Journal of Optics and Photonics
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• v.19 no.5
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• pp.376-380
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• 2008

This paper presents the Projection Moire method using a line scan camera. The high resolution feature of a line scan camera makes it possible to scan an image quickly, thus enabling a much quicker 3D profile. This method uses a high resolution line scan camera making it possible to scan an image at high speed simultaneously measuring the 3D profile of a large FOV. When using a high resolution scan camera, a full FOV is scanned, thus requiring just one movement of a projection grating. As a result, the number of grating movements is reduced drastically. The end result is a faster and more accurate 3D measurement. Moving the grating too quickly causes vibration in the imaging system, which will normally be required to apply a stitching technique when using an area scan camera. However the technique is not required when using a line scan camera. Compared with the previous techniques, it has the advantages of simple hardware without moving mechanical parts - single exposure for obtaining three-dimensional information. A method using a high resolution line scan camera can be used in mass production to measure the bump height of wafers or the bump height of package substrates.