• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.463-464
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• 2008

As the demands of LCD and PDP TV are increasing, the high performance HVICs(High Voltage Gate Driver ICs) technology is becoming more necessary. In this paper, we designed the HVIC that has enhanced noise immunity and high driving capability. It can operate at 500KHz switching frequency and permit 600V input voltage. High-side level shifter is designed with noise protection circuit and schmitt trigger. Therefore it has very high dv/dt immunity, the maximum being 50V/ns. The HVIC was designed using $1{\mu}m$ BCD 650V process and verified by Spectre and PSpice of Cadence inc. simulation.

• Journal of IKEEE
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• v.28 no.2
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• pp.204-208
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• 2024

In this paper, we propose an ESD protection circuit that applies structural changes to LVTSCR, a general low-voltage ESD protection circuit, to improve the current driving capability (IEC-ESD) characteristics of the ESD protection circuit. Power consumption was minimized by separating the area where the electric field and ESD current path are formed in the LVTSCR structure, and the electrical characteristics were analyzed and current driving characteristics were improved. Structural problems resulting from deterioration of system level characteristics were analyzed through simulation, and the characteristics were verified by reflecting this. The electrical characteristics of the proposed ESD protection circuit were verified using a TCAD simulator and analyzed through HBM modeling and system level modeling. In addition, silicon production and HBM 10kV characteristics were verified through DB-Hitek 0.18um BCD process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.105-112
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• 2009

In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.168-175
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• 2017

In this paper, a 5V small-area NMOS-diode eFuse OTP memory cell is proposed. This cell which is used in PMICs consists of a 5V NMOS transistor and an eFuse link as a memory part, based on a BCD process. Also, a regulated voltage of V2V ($=2.0V{\pm}10%$) instead of the conventional VDD is used to the pull-up loads of a VREF circuit and a BL S/A circuit to obtain a wider operational voltage range of the eFuse memory cell. When this proposed cells are used in the simulation, their sensing resistances are found to be $15.9k{\Omega}$ and $32.9k{\Omega}$, in the normal read mode and in the program-verify-read mode, respectively. Furthermore, the read current flowing through a non-blown eFuse is restricted to $97.7{\mu}A$. Thus, the eFuse link of a non-blown eFuse OTP memory cell is kept non-blown. The layout area of the designed 1kb eFuse OTP memory IP based on Dongbu HiTek's BCD process is $168.39{\mu}m{\times}479.45{\mu}m(=0.08mm^2)$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Radiation Oncology Journal
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• v.28 no.4
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• pp.231-237
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• 2010

Purpose: We investigated the effect of location changes in the inferior border of the belly board (BB) aperture by adding a bladder compression device (BCD). Materials and Methods: We respectively reviewed data from 10 rectal cancer patients with a median age 64 years (range, 45~75) and who underwent computed tomography (CT) simulation with the use of BB to receive pelvic radiotherapy between May and September 2010. A CT simulation was again performed with the addition of BCD since small bowel (SB) within the irradiated volume limited boost irradiation of 5.4 Gy using the cone down technique after 45 Gy. The addition of BCD made the inferior border of BB move from symphysis pubis to the lumbosacral junction (LSJ). Results: Following the addition of BCD, the irradiated volumes of SB and the abdominopelvic cavity (APC) significantly decreased ($174.3{\pm}89.5mL$ vs. $373.3{\pm}145.0mL$, p=0.001, $1282.6{\pm}218.7mL$ vs. $1,571.9{\pm}158mL$, p<0.001, respectively). Bladder volume within the treated volume increased with BCD ($222.9{\pm}117.9mL$ vs. $153.7{\pm}95.5mL$, p<0.001). The ratio of irradiated bladder volume to APC volume with BCD ($33.5{\pm}14.7%$) increased considerably compared to patients without a BCD ($27.5{\pm}13.1%$) (p<0.001), and the ratio of irradiated SB to APC volume decreased significantly with BCD ($13.9{\pm}7.6%$ vs. $24.2{\pm}10.2%$, p<0.001). The ratios of the irradiated SB volume and irradiated bladder volume to APC volume negatively correlated (p=0.001). Conclusion: This study demonstrated that the addition of BCD, which made the inferior border of BB move up to the LSJ, increased the ratio of the bladder to APC volume and as a result, decreased the irradiated volume of SB.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.3 no.2
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• pp.18-23
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• 1985

This paper develops a new theory of multi-valued switching functions and presents simplification method of the multi-valued combinational circuits for realizing N-valued arithmetic units. Multi-valued adders based on the theory proposed here is presented. Switching funtions to composite 10-valued arithmetic units with BCD input are described which is taken into account of using together with 2-valued logic systems.

• The Bulletin of The Korean Astronomical Society
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• v.38 no.2
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• pp.50.1-50.1
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• 2013

Blue Compact Dwarf galaxies (BCDs) are systems which have been experiencing the bursts of star formation in their central region. As one of the origins of active star formation, tidal interaction (merger or fly-by between dwarf galaxies) has been suggested. A pair of BCDs, ESO 435-IG20 and ESO 435-IG16, are suspected to be a good example of such case. They are located at a similar redshift and separated only by ~130 kpc at their distances. In addition a bridge-like HI structure has been found between these two BCDs in the HIPASS survey. In this study, using the ATCA HI data of a much better resolution, we probe the gas morphology and kinematics of individual galaxies. We discuss how tidal interaction is responsible for the high star formation rate in this BCD pair.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.8-13
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• 2005

In this paper discusses single-phase DC-AC Inverter design of reversible power converter that driven by binary combination at different transformer winding ratio by BCD code level. It has a advantage that constructs a control system simply and obtain load current of good quality without filter circuit and free from noise or isolation for lower switching frequency. In this research, study on current type converter and inverter circuit that consist for possibility of AC-DC/DC-AC multi-level reversible converter.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.784-787
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• 1999

The 74LS49 and 74LS47 chips are MSI circuits and are used for decoding the BCD input and driving seven-segment displays. The logic of these chips are often used not only as component chips in the commercial digital systems, but are used as library components in fairly complicated ASIC designs. Thus, the understanding of the logic characteristics of these chips is beneficial for future applications. It was analyzed reversely that the design of these chips includes a special logic minimization technique, which neither documented nor reported. This paper is to analyze the function of the logic and the special minimization technique adapted in the design of 74LS49 and 74LS47 chips.