• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.233-240
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• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• ETRI Journal
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• v.43 no.4
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• pp.684-693
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• 2021

This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.320-322
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• 2017

In this paper, a high-performance, low-area gradient-magnitude calculator architecture is proposed, based on approximate image processing. To reduce the computational complexity of the gradient-magnitude calculation, vector properties, the symmetry axis, and common terms were applied in a hardware-resource-shared architec-ture. The proposed gradient-magnitude calculator was implemented using an Altera Cyclone IV FPGA (EP4CE115F29) and the Quartus II v.16 device software. It satisfied the output-data quality while reducing the logic elements by 23% and the embedded multipliers by 76%, compared with previous work.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.8
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• pp.2881-2894
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• 2014

In complicated environment, context information plays an important role in image segmentation/labeling. The recently proposed auto-context algorithm is one of the effective context-based methods. However, the standard auto-context approach samples the context locations utilizing a fixed radius sequence, which is sensitive to large scale-change of objects. In this paper, we present a scale invariant auto-context (SIAC) algorithm which is an improved version of the auto-context algorithm. In order to achieve scale-invariance, we try to approximate the optimal scale for the image in an iterative way and adopt the corresponding optimal radius sequence for context location sampling, both in training and testing. In each iteration of the proposed SIAC algorithm, we use the current classification map to estimate the image scale, and the corresponding radius sequence is then used for choosing context locations. The algorithm iteratively updates the classification maps, as well as the image scales, until convergence. We demonstrate the SIAC algorithm on several image segmentation/labeling tasks. The results demonstrate improvement over the standard auto-context algorithm when large scale-change of objects exists.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.497-505
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• 2016

The two-dimensional (2D) Discrete Cosine Transform (DCT) is used widely in image and video processing systems. The perception of human visualization permits us to design approximate rather than exact DCT. In this paper, we propose a digital implementation of 16-point approximate 2D DCT architecture based on one-dimensional (1D) DCT and Modified Gate Diffusion Input (MGDI) technique. The 8-point 1D Approximate DCT architecture requires only 12 additions for realization in digital VLSI. Additions can be performed using the proposed 8 transistor (8T) MGDI Full Adder which reduces 2 transistors than the existing 10 transistor (10T) MGDI Full Adder. The Approximate MGDI 2D DCT using 8T MGDI Full adders is simulated in Tanner SPICE for $0.18{\mu}m$ CMOS process technology at 100MHZ.The simulation result shows that 13.9% of area and 15.08 % of power is reduced in the 8-point approximate 2D DCT, 10.63 % of area and 15.48% of power is reduced in case of 16-point approximate 2D DCT using 8 Transistor MGDI Full Adder than 10 Transistor MGDI Full Adder. The proposed architecture enhances results in terms of hardware complexity, regularity and modularity with a little compromise in accuracy.

• The KIPS Transactions:PartD
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• v.18D no.5
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• pp.323-328
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• 2011

For content-based image retrieval, the earth mover's distance and the optimal color composition distance are proposed to measure the dissimilarity. Although providing good retrieval results, both methods are too time-consuming to be used in a large image database. To solve the problem, we propose a new distance function that calculates an approximate earth mover's distance in linear time. To calculate the dissimilarity in linear time, the proposed approach employs the space-filling curve. We have performed extensive experiments to show the effectiveness and efficiency of the proposed approach. The results reveal that our approach achieves almost the same results with the EMD in linear time.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.284-287
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• 1998

It is important to develop a method of assembling a set of sub pictures automatically into a mosaic picture , because a view through fiberscopes or microscopes with higher magnifying power is much larger than the field of view taken by a camera. This paper presents a method of assembling sub pictures, where roughly estimated junctions called approximate junctions are employed for matching triangles formed by selected junctions in sub pictures. To over come the difficulties in processing speed and noise corruption, fuzzy rules is applied to get fuzzy values for existence of approximate junctions and fuzzy similarity for congruent triangle matching. Some demonstration, exemplified by assembling microscopic metal matrix photographs, are given to show feasibility of this method.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.969-970
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• 2006

This paper develops a recognition system of assembly parts using a hardware independent image module. Using a shared memory, the image module consists of the image acquiring process and the image processing process. We preprocess an acquisition image from the module, approximate the image edges to an ellipse, and then recognize an assembly part by matching the ellipse to a model base one.

• Journal of Korea Multimedia Society
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• v.20 no.2
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• pp.163-169
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• 2017

There are various algorithms evaluating a threshold for image segmentation. Among them, Otsu's algorithm sets a threshold based on the histogram. It finds the between-class variance for all over gray levels and then sets the largest one as Otsu's optimal threshold, so we can see that Otsu's algorithm requires a lot of the computation. In this paper, we improved the amount of computational needs by using estimated Otsu's threshold rather than computing for all the threshold candidates. The proposed algorithm is compared with the original one in computation amount and accuracy. we confirm that the proposed algorithm is about 29 times faster than conventional method on single processor and about 4 times faster than on parallel processing architecture machine.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.1
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• pp.43-54
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• 2000

Character-based trademarks constitute 90% of registered trademarks at the Korean Patent Office. This paper proposes a method to improve the precision rate when for similar trademarks in such systems. The proposed method first calculates the similarity measure by an image processing. The method has been implemented and merged with the existing device-mark retrieval system to improve precision rate by 16.2% compared to other approximate matching methods.