• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.5
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• pp.50-56
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• 1985

A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1154-1161
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• 2015

This paper presents a semi-lumped balun transformer using conventional PCB process and its design theory and geometry for the maximally flat response and wide bandwidth using magnetically coupled LC resonators. The proposed balun is comprised of two pairs of coupled resonators which share one among three LC resonators. It provides an identical magnitude and phase difference of 180° between two balanced ports with DC isolation and an impedance transformation characteristic. Theoretical design and analysis were performed to optimize the inductance and capacitance values of proposed balun device for obtaining the wide bandwidth and maximally flat response in its pass-band. Three balun transformers with a center frequency of 500 MHz were demonstrated for proving the concept of design proposed. They were fabricated by using lumped chip capacitors and planar inductors embedded into a conventional 4-layered PCB substrate. They exhibited a maximum magnitude difference of 0.8 dB and phase difference within 2.4 degrees.

• Journal of information and communication convergence engineering
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• v.3 no.4
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• pp.187-190
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• 2005

High aspect ratio via-hole etching process has emerged as one of the most crucial means to increase component density for ULSI devices. Because of charge accumulation in via-hole, this sophisticated and important process still hold several problems, such as etching stop and loading effects during fabrication of integrated circuits. Indeed, the concern actually depends on accumulated charge. For monitoring accumulated charge during plasma etching process, charge-up monitoring sensor was fabricated and tested under some plasma conditions. This paper presents a neural network-based technique for analyzing and modeling several electrical performance of plasma charge-up monitoring sensor.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.173-179
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• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.263-266
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• 1998

ZnO varistors have an excellent non-linearity and a large surge-energy absorption capability. For these reasons, the ZnO varistors are widely used to protect electrical/electronic circuits from an abnormal surge and/or noise signal. In order to obtain the low-voltage varistor with randomly distributed large seed grain within bulk, the ZnO varistors are made by a new three-composition seed grain method. And a conduction mechanism of varistors, which was observed in the temperature range of 30 ∼ 120$^{\circ}C$ and at the current range of 10$\^$-8/∼10$^2$ A/cm$^2$, was classified by the three regions of different mechanism when the current was increased.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.65-78
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• 2017

Single Event Transient has a critical impact on highly integrated logic circuits which are currently common in various commercial and consumer electronic devices. Reliability against the soft and intermittent faults will become a key metric to evaluate such complex system on chip designs. Our previous work analyzing soft errors was focused on parallelizing and optimizing error propagation procedures for individual transient faults on logic and sequential cells. In this paper, we present a new propagation technique where a fault binary decision diagram (BDD) continues to merge every new fault generated from the subsequent logic gate traversal. BDD-based transient fault analysis has been known to provide the most accurate results that consider both electrical and logical properties for the given design. However, it suffers from a limitation in storing and handling BDDs that can be increased in size and operations by the exponential order. On the other hand, the proposed method requires only a visit to each logic gate traversal and unnecessary BDDs can be removed or reduced. This results in an approximately 20-200 fold speed increase while the existing parallelized procedure is only 3-4 times faster than the baseline algorithm.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.79-85
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• 2016

In this study, we proposed a new single-stage small power MH lamp electronic ballast and power-factor correction circuit with improved circuit by the current of passive power factor correction. Main circuit integrates traditional DC/DC and DC/AC circuits into one-stage DC/AC inverter. Moreover, we described the working principle and control strategy of the new circuit; it's soft switching principle; and resonant element parameter design formula. An experimental prototype of HID lamp electronic ballast with output power of 70 W was built to verify the feasibility of the analysis and design. The simulation and experimental results proved that the power factor of this circuit could reach 94%, with efficiency of 90%. The input current harmonics conform to IEC 61000-3-2 standards and its cost is low. These superior performances of the new circuit indicate certain practical values.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.391-396
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• 2023

Recently, as power and electronic devices have increased in frequency and capacity, it has become a major concern to protect electronic circuits and electronic components used in these devices from abnormal voltages such as various surges and pulse noise. To respond to variously rated voltages applied to power electronic devices, the rated voltages of various varistors can be obtained by controlling the size of internal particles of the varistor or controlling the number of layers of the varistor. During bonding, the problem of unbalanced thermal runaway occurring between the electrode and the varistor interface causes degradation of the varistor and shortens its life of the varistor. In this study, to solve the problem of unbalanced heat distribution of stacked varistors to adjust the operating voltage, the contents of the ZnO-based varistor composition were 96 wt% ZnO, 1 mol% Sb₂O₃, 1 mol% Bi₂O₃, 0.5 mol% CoO, 0.5 mol% MnO, and 1 mol% TiO₂. A multi-layered ZnO varistor was modeled by bonding a single varistor with a composition in three layers according to the operating voltage. The thermal distribution of the triple-layered ZnO varistor was analyzed for the thermal runaway phenomenon that occurred during varistor operation using the finite element method according to Comsol 5.2.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.564-581
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• 2016

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.