JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design and Analysis of Efficient Parallel Hardware Prime Generators

  • Kim, Dong Kyue (Dept. of Electronic Engineering, Hanyang University) ;
  • Choi, Piljoo (Dept. of Electronic Engineering, Hanyang University) ;
  • Lee, Mun-Kyu (Dept. of Computer and Information Engineering, Inha University) ;
  • Park, Heejin (Dept. of Computer Science and Engineering, Hanyang University)
  • Received : 2015.10.22
  • Accepted : 2016.05.19
  • Published : 2016.10.30
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Abstract

We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.

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