• ETRI Journal
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• v.26 no.4
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• pp.315-320
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• 2004

This paper proposes a 10-${\mu}m$ thick oxide layer structure that can be used as a substrate for RF circuits. The structure has been fabricated using an anodic reaction and complex oxidation, which is a combined process of low-temperature thermal oxidation (500 $^{\circ}C$ for 1 hr at $H_2O/O_2$) and a rapid thermal oxidation (RTO) process (1050 ${\circ}C$, for 1 min). The electrical characteristics of the oxidized porous silicon layer (OPSL) were almost the same as those of standard thermal silicon dioxide. The leakage current density through the OPSL of 10 ${\mu}m$ was about 10 to 50 $nA/cm^2$ in the range of 0 to 50 V. The average value of the breakdown field was about 3.9 MV/cm. From the X-ray photo-electron spectroscopy (XPS) analysis, surface and internal oxide films of OPSL prepared by a complex process were confirmed to be completely oxidized. The role of the RTO process was also important for the densification of the porous silicon layer (PSL) oxidized at a lower temperature. The measured working frequency of the coplanar waveguide (CPW) type short stub on an OPSL prepared by the complex oxidation process was 27.5 GHz, and the return loss was 4.2 dB, similar to that of the CPW-type short stub on an OPSL prepared at a temperature of 1050 $^{\circ}C$ (1 hr at $H_2O/O_2$). Also, the measured working frequency of the CPW-type open stub on an OPSL prepared by the complex oxidation process was 30.5 GHz, and the return was 15 dB at midband, similar to that of the CPW-type open stub on an OPSL prepared at a temperature of $1050^{\circ}C$ (1 hr at $H_2O/O_2$).

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.470-470
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• 2013

Recently, active materials such as amorphous silicon (a-Si), poly crystalline silicon (poly-Si), transition metal oxide semiconductors (TMO), and organic semiconductors have been demonstrated for flexible electronics. In order to apply flexible devices on the polymer substrates, all layers should require the characteristic of flexibility as well as the low temperature process. Especially, pentacene thin film transistors (TFTs) have been investigated for probable use in low-cost, large-area, flexible electronic applications such as radio frequency identification (RFID) tags, smart cards, display backplane driver circuits, and sensors. Since pentacene TFTs were studied, their electrical characteristics with varying single variable such as strain, humidity, and temperature have been reported by various groups, which must preferentially be performed in the flexible electronics. For example, the channel mobility of pentacene organic TFTs mainly led to change in device performance under mechanical deformation. While some electrical characteristics like carrier mobility and concentration of organic TFTs were significantly changed at the different temperature. However, there is no study concerning multivariable. Devices actually worked in many different kinds of the environment such as thermal, light, mechanical bending, humidity and various gases. For commercialization, not fewer than two variables of mechanism analysis have to be investigated. Analyzing the phenomenon of shifted characteristics under the change of multivariable may be able to be the importance with developing improved dielectric and encapsulation layer materials. In this study, we have fabricated flexible pentacene TFTs on polymer substrates and observed electrical characteristics of pentacene TFTs exposed to tensile and compressive strains at the different values of temperature like room temperature (RT), 40, 50, $60^{\circ}C$. Effects of bending and heating on the device performance of pentacene TFT will be discussed in detail.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.651-656
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• 2014

This paper analyzed the change of subthreshold swing for channel doping of asymmetric double gate(DG) MOSFET. The subthreshold swing is the factor to describe the decreasing rate of off current in the subthreshold region, and plays a very important role in application of digital circuits. Poisson's equation was used to analyze the subthreshold swing for asymmetric DGMOSFET. Asymmetric DGMOSFET could be fabricated with the different top and bottom gate oxide thickness and bias voltage unlike symmetric DGMOSFET. It is investigated in this paper how the doping in channel, gate oxide thickness and gate bias voltages for asymmetric DGMOSFET influenced on subthreshold swing. Gaussian function had been used as doping distribution in solving the Poisson's equation, and the change of subthreshold swing was observed for projected range and standard projected deviation used as parameters of Gaussian distribution. Resultly, the subthreshold swing was greatly changed for doping concentration and profiles, and gate oxide thickness and bias voltage had a big impact on subthreshold swing.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.91-103
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• 2015

This paper presents "The 3-User NOR switching channel based on interference decoding with receiver cooperation" in succession to "Jeju Jong Nang channel code I, II". The Jeju Jong Nang code is considered as one of the earliest human binary coded communication (HBCC) in the world with a definite "1" or "0" binary symbolic analysis of switching circuits. In this paper, we introduce a practical example of interference decoding with receiver cooperation based on the three user Jong Nang NOR switching channel. The proposed system models are the three user Jong Nang (TUJN) NOR logic switching on-off, three-user injective deterministic NOR switching channel and Gaussian interference channel (GIC) with receiver cooperation. Therefore, this model is well matched to Shannon binary symmetric and erasure channel capacity. We show the applications of three-user Gaussian interference decoding to obtain deterministic channels which means each receiver cooperation helps to adjacent others in order to increase degree of freedom. Thus, the optimal sum rate of interference mitigation through adjacent receiver cooperation achieves 7 bits.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.147-151
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• 2017

Areas of concentrations that can be exploited at all times, such as gas reservoirs in crude oil tanks, are called zero zones. In order to use various equipment in Zone 0, an intrinsically safe certification must be obtained that can guarantee that sparks will not occur in nature. Most devices that acquire intrinsic safety certification are mostly simple single-component devices or devices. In this study, it was a very difficult process because we intend to acquire the intrinsic safety certification of an electronic circuit including an ultrasonic generator and a microcontroller in which hundreds of components are mounted on a PCB substrate. Through this study, we have been able to understand how to design a circuit for intricate intrinsic safety certification. and Using the results of this study, it will be easier to design intrinsically safe circuits when trying to develop a circuit that can obtain intrinsic safety certification.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.2
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• pp.189-194
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• 2018

Nowadays most integrated circuits are built using the bulk CMOS technology, but it has much difficulty in further reduction of the power consumption and die size. As a super low-power technology to solve such problems, the SOI technology attracts great attention recently. In this paper, the study results of the temperature dependency of the hot carrier effects in the n-channel MOSFETs fabricated on the thin SOI substrate were discussed. In spite that the devices employed the LDD structure, the hot carrier effects were more serious than expected due to the high series resistance between the channel region and the substrate contact to the ground, and were found to be less serious for the higher temperature with the more phonon scattering in the channel region, which resulted in reducing the hot electron generation.

• Journal of IKEEE
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• v.24 no.3
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• pp.803-813
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• 2020

This paper presents a high efficiency resonant flyback converter using a single-chip microcontroller. The proposed converter primary performs the resonant switching by applying the asymmetrical pulse-width modulation (APWM) to the half-bridge power topology. And the converter secondary uses the diode flyback rectifier as its power topology and operates with the zero current switching (ZCS). Thus the proposed converter achieves high efficiency. The total structure of proposed converter is very simple because it uses a single-chip microcontroller and bootstrap circuit for its control and drive, respectively. First, this paper describes the converter operation according to each operation mode and shows its steady-state analysis. And the software control algorithm and drive circuits operating the proposed converter are explained. Then, the operation characteristics of proposed converter are shown through the experimental results of an implemented prototype based on each explanation.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.