• Title/Summary/Keyword: Analog-to-Digital(A/D)

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A Class-D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

  • Lee, Dongjun;Noh, Jinho;Lee, Jisoo;Choi, Yongjae;Yoo, Changsik
    • ETRI Journal
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    • v.35 no.5
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    • pp.819-826
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    • 2013
  • A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

Design of 6bit CMOS A/D Converter with Simplified S-R latch (단순화된 S-R 래치를 이용한 6비트 CMOS 플래쉬 A/D 변환기 설계)

  • Son, Young-Jun;Kim, Won;Yoon, Kwang-Sub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.11C
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    • pp.963-969
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    • 2008
  • This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

A 9-Bit 80-MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique

  • Lee, Seung-Chul;Jeon, Young-Deuk;Kwon, Jong-Kee
    • ETRI Journal
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    • v.29 no.3
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    • pp.408-410
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    • 2007
  • A 9-bit 80-MS/s CMOS pipelined folding analog-to-digital converter employing offset-canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc-decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ${\pm}0.6$ LSB and ${\pm}1.6$ LSB, respectively.

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Co-Simulation for Systematic and Statistical Correction of Multi-Digital-to-Analog-Convertor Systems

  • Park, Youngcheol;Yoon, Hoijin
    • Journal of electromagnetic engineering and science
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    • v.17 no.1
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    • pp.39-43
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    • 2017
  • In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

An Architecture Design of a Multi-Stage 12-bit High-Speed Pipelined A/D Converter (다단 12-비트 고속 파이프라인 A/D 변환기의 구조 설계)

  • 임신일;이승훈
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.220-228
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    • 1995
  • An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.

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Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System

  • Rho, Sung-Chan;Lim, Shin-Il
    • IEIE Transactions on Smart Processing and Computing
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    • v.4 no.3
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    • pp.189-193
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    • 2015
  • This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

A 4×32-Channel Neural Recording System for Deep Brain Stimulation Systems

  • Kim, Susie;Na, Seung-In;Yang, Youngtae;Kim, Hyunjong;Kim, Taehoon;Cho, Jun Soo;Kim, Jinhyung;Chang, Jin Woo;Kim, Suhwan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.1
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    • pp.129-140
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    • 2017
  • In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

A Design of Pipelined Analog-to-Digital Converter with Multi SHA Structure (Multi SHA 구조의 파이프라인 아날로그-디지털 변환기 설계)

  • Lee, Seung-Woo;Ra, Yoo-Chan;Shin, Hong-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2A
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    • pp.114-121
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    • 2005
  • In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

Design of a Portable Digital Pressure Algometer (휴대용 디지털 압통기의 설계)

  • 송미혜;박호동;이경중;권오윤
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.11
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    • pp.657-661
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    • 2003
  • In this paper, we designed a portable digital pressure algometer which not only can measure the pain level objectively and quantitatively, but also is able to do RF communication. This system consists of pressure sensor for pain measurement, analog signal analysis, digital hardware based on PIC16C73B, RF communication and display. To evaluate the performance of the developed system, we measured pressure threshold using commercial analog PA(Pressure Algometer) and the proposed system, and then evaluated the correlation and confidence. Using linear regression analysis, standard deviation of 0.1731 and R-square value of 99.3% were obtained. In conclusion, the above results showed good performance and its usability in measuring the pain clinically.

Quantization error model of signal converter in strapdown inertial navigation system (스트랩다운 관성항법장치의 신호변환기 양자화 오차모델)

  • 정태호;송기원
    • 제어로봇시스템학회:학술대회논문집
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    • 1991.10a
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    • pp.131-135
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    • 1991
  • A quantization error model is suggested for analog to frequency(A/F) converter in strapdown inertial navigation system(SDINS),which is characterized by some white noise exciting the state variables. Also, effects on the performance of SDINS by analog to digital(A/D) converter and A/F converter are analyzed and compared via covariance simulation. As a result, A/F converter turns out to be superior to the A/D converter with respect to the induced navigation error and the difficulty in circuit realization. The quantization error model developed in this paper appears to be useful for optimal filter design.

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