• 제어로봇시스템학회논문지
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• 제17권4호
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• pp.289-294
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• 2011

Digital redesign is yet another efficient tool to convert a pre-designed analog controller into a sampled-data one to maintain the analog closed-loop performance in the sense of state matching. A rising difficulty in developing a digital redesign technique for trackers with time-varying references is the unavailability of a closed-form discrete-time model of a system, even if it is linear time-invariant. A way to resolve this is to approximate the time-varying reference as a piecewise constant one, which deteriorates the state matching performance. Another remedy may be to decrease a sampling period, which however could numerically destabilize the optimization-based digital redesign condition. In this paper, we develop a digital redesign condition for time-varying trackers by approximating the time-varying reference through a triangular hold and by introducing delta-operated discrete-time models. It is shown that the digitally redesigned sampled-data tracker recovers the performance of the pre-designed analog tracker under a fast sampling limit. Simulation results on the formation flying of satellites convincingly show the effectiveness of the development.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1173-1176
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권11호
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• 한국정보통신학회논문지
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• 제25권11호
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• pp.1619-1626
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• 2021

증분형 아날로그 디지털 변환기는 전통적인 델타 시그마 아날로그 디지털 컨버터와 달리 리셋 동작을 통한 입력과 출력의 1:1 매핑이 가능하며 이는 멀티플렉싱에 매우 용이하게 사용될 수 있다. 또한, 증분형 아날로그 디지털 변화기는 전통적인 델타 시그마 변환기에 비해 간단한 디지털 필터 설계가 가능하다. 따라서, 본 논문에서는 아날로그 디지털 컨버터 설계에 기본이 되는 딜레이가 있는 적분기와 딜레이가 없는 적분기의 시간 영역에서의 분석을 시작으로 2차 입력 피드 포워드, 확장된 카운팅, 2+1 매쉬, 2+2 매쉬 구조를 갖는 증분형 아날로그 디지털 변환기의 설계 방정식을 유도한다. 이를 통해 설계 이전에 증분형 아날로그 디지털 변환기의 성능을 예측할 수 있을 뿐만 아니라 각각의 아날로그 디지털 변화기에 적합한 디지털 필터를 설계할 수 있다. 또한, 아날로그 디지털 변환기의 정확도를 향상 시키기 위한 확장된 카운팅, MASH의 설계 기술들을 제안하였다.

• 전자공학회논문지SC
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• 제47권3호
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• pp.13-18
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• 2010

본 논문은 디스플레이 데이터 구동부에 사용되는 디지털 아날로그 컨버터를 위해 스위치 커패시터형 cyclic 디지털 아날로그 컨버터를 제안하고 특성을 검토한다. 본 제안의 디지털 아날로그 컨버터는 구성이 간단하여 저전력, 소면적의 디스플레이 구동 IC설계에 적합하다. 회로레벨 시뮬레이션을 통해 OP앰프 입력의 오프셋전압에 대한 영향이 적고 커패시터간의 부정합이 0.5% 정도까지는 회로성능에 별 영향이 없음을 검증한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.647-654
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• 2013

The design and analysis of analog circuit application on CMOS technology are a challenge in deep sub-micrometer process. This paper is a study on the performance value of Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with Gate Stack and the channel engineering Single Halo (SH), Double Halo (DH). Four different structures have been analysed keeping channel length constant. The short channel parameters and different sub-threshold analog figures of merit (FOMs) are analysed. This work extensively provides the device structures which may be applicable for high speed switching and low power consumption application.

• 대한임베디드공학회논문지
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• 제4권1호
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• pp.23-28
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• 2009

Testing of analog(and mixed-signal) circuits has been a difficult task for test engineers and effective test techniques to solve these problems are required. This paper develops a new technique which increases fault detection and diagnosis rates for analog circuits by using extended MTSS (Modified Time Slot Specification) technique based on MTSS proposed by the author. High performance current sensors with digital outputs are used as core components for these techniques. A fault diagnosis structure with minimal hardware overhead in ATE is also described.

• Journal of Power Electronics
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• 제6권2호
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• pp.139-145
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• 2006

This paper describes the ultra precise position estimation of a servomotor using a sinusoidal encoder based on Arcsine Interpolation Method for the cost reduction of circuit design. The amplitude and offset errors of the sinusoidal encoder output signals, from the encoder itself and analog signal processing procedures, are effectively compensated and on-line tuned by utilizing a low cost programmable differential amplifier without any special expensive equipment. For a theoretical evaluation of the practical resolution of this system, the relationship between the amplitude of ADC(Analog to Digital Converter) input signal errors and the anticipated resolution is also addressed. The performance of the proposed method is verified by comparing it with speed control characteristics of the servomotor driving system using a digital incremental 50,000ppr encoder in the experiments.