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멀티미디어 통신용 병렬 아키텍쳐 고속 비터비 복호기 설계
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[
이병철;선우명훈
] /
대한 전자 공학회 논문지
과학기술학회마을
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N. Sohi, P. G. Culak, 'A multistandard set-up box channel decoder,' in IEEE Workshop Signal Processing System(SiPS), Lafayette, LA, Oct. 2000, pp. 295-304
|
3 |
J. A. Heller, J. M. Jacobs, 'Viterbi decoding for satellite and space communication,' IEEE Trans. Commun. Technol., vol. COM-19, pp. 835-848, Oct. 1971
DOI
ScienceOn
|
4 |
Kang, A. N. Wilson, Jr., 'Low-power Viterbi decoder for CDMA mobile terminals,' IEEE J. Solid-State Circuits, vol. 33, pp. 473-482, Mar, 1998
DOI
ScienceOn
|
5 |
T. W. Matthews, R. R. Spencer, 'An intergrated analog CMOS Viterbi detector for digital magnetic recoding,' IEEE J. Solid-State Circuits, vol. 28, pp. 1294-1302, Dec. 1993
DOI
ScienceOn
|
6 |
Kai He and Gert Cauwenberghs, 'Integrated 64-state parallel analog Viterbi decoder,' Proceedings of ISCAS 2000, Geneva, Swiss, vol. IV, pp. 761-764
DOI
|
7 |
G. David Forney, JR. 'The Viterbi Algorithm,' Proc. of the IEEE, vol. 61, No. 3, Mar. 1973
|
8 |
P. G. Gulakand E. Shwedyk. 'VLSI structures for viterbi receivers: Part I - general theory and applications,' IEEE J. on Selected areas in comm., vol. 4, pp. 142-154, Jan. 1986
DOI
|
9 |
Jens Sparso, Henrik N., Jorgenson, 'An Area-Efficient Toplology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures,' IEEE Jr. Solid-State Circuit, vol. SC-26, no. 2, pp. 90-96, Feb. 1991
DOI
ScienceOn
|
10 |
M. Moerz, A. Schaefer, 'Analog decoders for high rate convolutional codes,' IWT 2001, Australia, pp. 128-130
DOI
|
11 |
I. Baturone, J.L. Huertas, A. Barriga and S. Sanchez-Solano, 'Current-mode multiple-input Max circuit,' Electronics Letters, vol. 30, no. 9, Apr. 1994
DOI
ScienceOn
|
12 |
김성원, 김종만, 김형석, '측방향정보전파신경회로망 IC설계,' CAD 및 VLSI 설계연구회지, 제6권 제1호, pp. 89-101, 1997. 12
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이병철, 선우명훈, '멀티미디어 통신용 병렬 아키텍쳐 고속 비터비 복호기 설계,' 대한 전자 공학회 논문지, vol. 37, no. 2, pp. 78-84, 2000. 2
과학기술학회마을
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