• 전기학회논문지
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• 제59권8호
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• pp.1489-1496
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• 2010

A feed forward differential architecture of analog PRML decoder is investigated to implement on analog parallel processing circuits. The conventional PRML decoder performs the trellis processing with the implementation of single stage in digital and its repeated use. The analog parallel processing-based PRML comes from the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Shortening the trellis processing stages but implementing it with analog parallel circuits, several benefits including higher speed, no memory requirement and no A/D converter requirement are obtained. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback of the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from all the states of the decoding stage, which enables to be decoded without feedback. The circuit of the proposed architecture is simpler than that of the conventional analog parallel processing structure with the similar decoding performance. Characteristics of the feed forward differential architecture are investigated through various simulation studies.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.375-377
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• 2006

A Analog parallel processing-based Viterbi decoder which decodes PRML signal of DVD has been designed by CMOS circuit. The analog processing-based Viterbi decoder implements are functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The Analog parallel processing-based Viterbi decoding technology is applied for the PR(1,2,2,1) signal decoding of DVD. The benefits are low power consumption and less silicon consumption. In this paper, the comparison of the Analog parallel processing-based Viterbi Decoder which has a function of the error correction between Max operation and Average operation is discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.378-380
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• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• 전기학회논문지P
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• 제58권4호
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• pp.623-626
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• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권7호
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• pp.465-472
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• 2004

Analog CPPN-based optimal road boundary detection algorithm for autonomous vehicle is proposed. The CPPN is a massively connected analog parallel array processor. In the paper, the dynamic programming which is an efficient algorithm to find the optimal path is implemented with the CPPN algorithm. If the image of road-boundary information is utilized as an inter-cell distance, and goals and start lines are positioned at the top and the bottom of the image, respectively, the optimal path finding algorithm can be exploited for optimal road boundary detection. By virtue of the parallel and analog processing of the CPPN and the optimal solution of the dynamic programming, the proposed road boundary detection algorithm is expected to have very high speed and robust processing if it is implemented into circuits. The proposed road boundary algorithm is described and simulation results are reported.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.38-46
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• 2006

DVD용 PRML신호를 디코딩할 수 있는 병렬 아날로그 비터비 디코더를 칩으로 제작하고 테스트 결과를 기술하였다. 병렬 아날로그 비터비 디코더는 기존의 디지털 비터비 디코더를 아날로그 병렬처리 회로를 이용하여 구현한 것으로, 전력 소모가 매우 적다는 장점이 있다. 본 연구에서는 제안한 순환형 아날로그 비터비 디코더 회로를 DVD의 PRML 신호 디코딩용으로 설계 제작하였고, 그 상세 설계 내용과 각 회로의 신호 특성을 분석하였으며, 이를 기반으로 향후 개선 사항을 기술하였다. 또한, 칩으로 제작된 회로가 동작하여 PRML용 신호가 잘 디코딩됨을 보였다.

• 전자공학회논문지CI
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• 제40권1호
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• pp.1-9
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• 2003

CNN-UM의 아날로그 연산기능을 활용할 수 있는 영상 변화 검출 알고리즘을 개발하였으며 이를 이동물체 검출에 활용하였다. CNN-UM은 영상의 아날로그 병렬처리가 가능한 구조이므로 고속의 실시간 처리가 필요한 분야에는 매우 높은 응용성을 가진 새로운 구조의 아날로그 및 로직처리(아나로직) 프로세서이다. 이 CNN-UM은 동일 영상 프레임 내에서의 처리에는 능률적인 구조이지만 영상 프레임 간의 계산에는 아날로그 병렬처리 기능을 활용하기 어려운 연산구조라는 단점이 있었다. 본 연구에서는 셀의 상태 저장 커패시터에 인접 프레임의 영상들을 상호 역 부호를 통하여 중첩함으로써 영상 프레임 간의 변화 검출을 병렬로 수행할 수 있는 알고리즘을 개발하였으며 이 원리를 전기적 등가회로를 통해 해석하였다. 또한, 개발한 알고리즘을 이동물체 검출을 위한 프레임간의 영상 변화 검출에 적용하여 타당성을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 춘계학술대회 논문집
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• pp.3-3
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• 2010

The Characteristics of Digital Vterbi Decoder utilizing the analog parallel processing circuit technology is proposed. The Analog parallel structure of the viterbi decoder acted by a replacement of the conventional digital viterbi Decoder is progressing fastly. The proposed circuits design han, low distortion, high accuracy over the previous implementation and dynamic programming.