• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.381-389
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• 2015

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a $0.18-{\mu}m$ CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.249-256
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• 2009

As a wireless handset deals with multiple application standards concurrently, RF transmitters and power amplifiers are required to be more power efficient and reconfigurable. In this paper, we review the recent advances in the design of the power amplifiers and transmitters. Then, the systematic design approaches to improve the performance with the digital baseband signal processing are introduced for the next generation mobile handset.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Proceedings of the KOSOMBE Conference
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• v.1994 no.12
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• pp.178-180
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• 1994

We developed a prototype force plate equipped with five load cells, a 12-bit analog-to-digital converter and three integrated circuits. The force plate displays the center of foot pressure, the magnitude and two (vertical and anterior-posterior) directions of the ground reaction force on a personal computer monitor. Although the force plate data are valid only for two directions, it can be a preliminary version of a more versatile 3 dimensional force plate in terms of the resolution and reliability.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1243-1246
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• 2006

A new source follower circuit for the integrated circuit of AMLCDs is proposed. Active load is added and calibration operation is applied to compensate the circuits. Proposed circuit is capable of minimizing the variation from both timing and device variations through measured results, the uniformity and bias effect are discussed.

• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.842-846
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• 2016

This paper presents a DC-DC buck converter which uses a sleep control to improve the power efficiency in a few mW light load condition. The sleep control turns off analog controller building blocks to reduce the static power losses during the off-duty period of pulse width modulation. For verification, a buck converter has been implemented in a $0.18{\mu}m$ CMOS process. The power efficiency has been improved from 76.7% to 82.5% with a 1.2 mW load. The maximum power efficiency is 95% with a 9 mW load.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.197-200
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• 2002

We newly developed the procedures of X-ray Cargo inspection system with acquisition of multi-channel data, analog to digital converter and post logic circuit which is controlled by the FPGA. The IEEE1149.1 standard defines a four-wire serial interface(a fifth wire is optional)to access complex integrated circuits(ICs) such as PLD. This paper describes that Boundary_Scan test method applied to our home made cargo inspection system.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.521-524
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• 1990

There is an increasing interest in high-speed signal processing in modern telecommunication and consumer electronics applications. HDTV, ISDN. A limiting factor in Op-Amp based analog integrated circuits is the limited useful frequency range. This research program will develop a new CMOS Op-Amp architecture with improved gainband width product. The new design CMOS Op-Amp will achieve up to 100MHz unity gainband width with a 1.5-micron design rule.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.11
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• pp.943-950
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• 2008

A novel nondestructive testing (NDT) system, which is able to detect a crack with high speed and high spatial resolution, is urgently required for inspecting small cracks on express train wheels. This paper proposes a high speed scan type magnetic camera, which uses the multiple amplifying circuits and the crack indicating pulse output system. The linearly integrated Hall sensors are arrayed in parallel, and the Hall voltages from each sensor in the scanning direction are obtained and amplified. High-speed NDT can be achieved by using the exclusive analog-digital converter and micro-processor because the ${\partial}\;V_H/\;{\partial}$ x value, which provides the most important crack information, can be obtained by buffering and calculating. The effectiveness of the novel method was verified by examine using cracks on the wheel specimen model.