• ETRI Journal
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• v.26 no.6
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• pp.560-564
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• 2004

An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a $0.25{\mu}m$ double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.66-71
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• 2014

This paper presents an analog front-end integrated circuit (IC) for medical ultrasound imaging systems using standard $0.18-{\mu}m$ CMOS process. The proposed front-end circuit includes the transmit part which consists of 15-V high-voltage pulser operating at 2.6 MHz, and the receive part which consists of switch and a low-power low-noise preamplifier. Depending on the operation mode, the output driver in the transmit pulser can be reconfigured as the switch in the receive path and thus the area of the overall front-end IC is reduced by over 70% in comparison to previous work. The designed single-channel front-end prototype consumes less than $0.045mm^2$ of core area and can be utilized as a key building block in highly-integrated multi-array ultrasound medical imaging systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• IT SoC Magazine
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• s.19
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• pp.37-42
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• 2007

이 글은 당사에서 개발 진행한 TDMB,ISDB-T등의 Moblie TV Receiver단의 Analog Front-End SIP들의 Test H/W, S/W제작 경험을 바탕으로 보다 효율적이고 성공적인 SIP 개발이 될 수 있도록 도움을 주고자 기술 하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.15-18
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• 2013

This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.77-86
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• 2010

In this paper, we present a noncoherent IR-UWB (Impulse Radio-Ultra Wide Band) ranging system with an AFE (Analog Front End) composed of a simple integrator and an 1-bit ADC (Analog-to-Digital Converter), and define AFE characteristics affecting the ranging performance. This system is realistic and easy to implement, since the integrator simply accumulates signal energies and the simple 1-bit ADC is applied instead of the multi-bit ADCs for coherent IR-UWB systems. On the other hand, its ranging accuracy is largely affected channel environments such as noise, multipath fading and so on, since the noncoherent receiver simply squares and integrates the received signals. However, despite these practical importances, there are few conventional researches on the performance analysis according to AFE characteristics in IR-UWB ranging systems. To this end, we analyze in this paper ranging performance according to AFE characteristics for the noncoherent IR-UWB ranging system in various wireless channel environments, and through these results we also present system parameters to be considered in UWB hardware designs.

• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• Journal of information and communication convergence engineering
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• v.18 no.4
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• pp.254-259
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• 2020

Phased-array antennas comprise a demanding antenna design methodology for commercial wireless communication systems or military radar systems. In addition to these two important applications, the phased-array antennas can be used in beamforming for wireless charging. In this study, a four-way analog beamforming front-end module (FEM) for a hybrid beamforming system is developed for 2.4 GHz operation. In a hybrid beamforming scheme, an analog beamforming FEM in which the phase and amplitude of RF signal can be adjusted between the RF chain and phased-array antenna is required. With the beamforming and beam steering capability of the phased-array antennas, wireless RF power can be transmitted with high directivity to a designated receiver for wireless charging. The four-way analog beamforming FEM has a 32 dB gain dynamic range and a phase shifting range greater than 360°. The maximum output RF power of the four-way analog beamforming FEM is 40 dBm (=10 W) when combined the four individual RF paths are combined.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.