• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.43-51
• /
• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.11
• /
• pp.48-55
• /
• 2016

Ambient-light sensor system, which changes the brightness of a display as ambient light change, was studied to reduce the power consumption of the mobile applications such as note PC, tablet PC and smart phone. The ambient-light sensor system should be integrated on a display panel to improve the complexity and cost of mobile applications, so the ambient-light sensor and readout circuit was integrated on a display panel using low-temperature poly-silicon thin film transistors (LTPS-TFT). We proposed the new compensation method to correct the panel-to-panel variation of the ambient-light sensors, without additional equipment. We designed and investigated the new readout circuit with the proposed compensation method and the analog-to-digital converter for the final digital output of ambient light. The readout circuit has very simple structure and control timing to be integrated with LTPS-TFT, and the input luminance ranges from 10 to 10,000 lux. The readout rate is 100 Hz, and maximum differential non-uniformity with 20 levels of the final output below 0.5 LSB.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1417-1422
• /
• 2005

Among the sensors mainly used for displacement measurement, there are a linear CCD(Charge Coupled Device) and a PSD(Position Sensitive Detector) as a non-contact type. Their structures are different very much, which means that the signal processing of both sensors should be applied in the different ways. Most of the displacement measurement systems to get the 3-D shape profile of an object using a linear CCD are a computer-based system. It means that all of algorithms and mathematical operations are performed through a computer program to measure the displacement. However, in this paper, the developed system has microprocessor and other digital components that make the system measure the displacement of an object without a computer. The thing different from the previous system is that AVR microprocessor and FPGA(Field Programmable Gate Array) technology, and a comparator is used to play the role of an A/D(Analog to Digital) converter. Furthermore, an ATC(Automatic Threshold Control) algorithm is applied to find the highest pixel data that has the real displacement information. According to the size of the light circle incident on the surface of the CCD, the threshold value to remove the noise and useless data is changed by the operation of AVR microprocessor. The total system consists of FPGA, AVR microprocessor, and the comparator. The developed system has the improvement and shows the better performance than the system not using the ATC algorithm for displacement measurement.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.5
• /
• pp.1-9
• /
• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of the Institute of Convergence Signal Processing
• /
• v.9 no.1
• /
• pp.54-61
• /
• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.10a
• /
• pp.420-423
• /
• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.

• The KIPS Transactions:PartA
• /
• v.15A no.6
• /
• pp.317-324
• /
• 2008

In this paper, we propose a system which easily controls the existing serially connected multi-channel speakers in a general personal computer by using a USB(Universal Serial Bus) interface. The personal computer as a host of the USB interface analyzes a sound source and sends audio data in a real-time fashion by the use of the isochronous transmission, one of four transmission methods provided by the USB interface. In addition, a channel is assigned by means of the bulk transmission, one of four transmission methods provided by the USB interface. Transmitted data from the USB host are sent to each speaker through compression and packet generation process. Each speaker detects corresponding digital data and regenerates audio signals through DAC(Digital-to-Analog Converter). A user can easily select a sound source file and a channel by the use of a GUI environment in a personal computer.

• Nuclear Engineering and Technology
• /
• v.53 no.10
• /
• pp.3406-3412
• /
• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• Journal of Advanced Navigation Technology
• /
• v.23 no.2
• /
• pp.97-103
• /
• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.5
• /
• pp.568-573
• /
• 2019

Modern Radars are evolving into MFRs which can search multiple targets simultaneously and then track them. Additionally they should be able to avoid some external jamming signals. Applying to these MFRs, Antennas should be able to perform DBF including to not only real-time beam steering but also multi-beam forming simultaneously. And they can cancel the beam at the specific direction. In this paper, we describe the implementation of sub-array type antenna hardware which can be applying DBF. Also we propose the modified amplitude aperture distribution for suppressing the side lobe level and explain the sub-array receiver design with amplitude tapering. It consists in making the amplitude weighting in 2 steps. In order to compare two weighting cases, we investigate the G/T performance for the array antenna. At the conclusion, we make a comparative study for the dynamic range of every sub-array receiver and present the hardware implementation that is more advantageous for sub-array alignment and calibration in DBF.