• ETRI Journal
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• 제31권2호
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• pp.209-214
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• 2009

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece-wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.81-84
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• 2004

Required characteristics of poly-Si TFT's are investigated for the implementation of analog circuits to be integrated on System-on-Glass (SoG). Matching requirements on resistor values, threshold voltage and mobility of poly-Si TFT's are derived as a function of the resolution of display system. Effective mobility of poly-Si TFT's required for the realization of source driver is analyzed for various panel sizes.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.1402-1405
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• 1993

In this paper, a fault evaluation method is proposed, which is to determine whether analog electronic circuits are faulty or not. In our method, evaluation characteristics of an expert test engineer are defined by means of directed graphs. By performing a multi-stage fuzzy inference based on the graphs, novice test engineers can derive a fault evaluation result satisfied by the expert. The effectiveness of our method is checked by some experiments for an amplifier circuit.

• 대한전자공학회논문지SD
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• 제43권1호
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• pp.17-26
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• 2006

DVD용 아날로그 read channel에 사용되는 PR (1 2 2 1) 신호용 아날로그 비터비 디코더를 순환형 아날로그 병렬회로망 구조를 이용하여 설계하였다. 고 밀도의 마그네틱 기록매체나 DVD등은 인접 신호들의 영향을 많이 받게 되므로, 상호 간섭된 심볼 코드를 일정한 규칙에 따라 생성시켜 코딩하며, 재생 시에는 코딩 규칙의 부합도에 따라 디코딩하여 재생오류를 최소화 시키는 기술이 PRML이다. 이 PRML기술은 주로 디지털 기술로 구현하여 사용되고 있으나, 보다 고속 저 전력화 필요가 증대하여 최근 아날로그 기술로 구현하는 방법이 활발하게 연구되고 있다. 본 연구는 DVD read channel의 아날로그 PRML 구현에 관한 연구로서 PRML의 고속화에 가장 어려운 부분인 비터비 디코더 부분을 순환형 아날로그 병렬 회로망 구조를 이용하여 설계하였다. 설계한 PRML용 비터비 디코더는 PR (1 2 2 1) type으로 기존의 디지털 비터비 디코더 속도의 3배, 전력소모의 1/3인 성능을 보였다.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.131-134
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• 2002

In this work, we have developed a systematic way of utilizing the basic design tools for superconductive electronics. This include WRSPICE, XIC, margin program, and L-meter. Since the high performance analog-to- digital converter can be built with Rapid Single Flux Quantum (RSFQ) logic circuits the development of superconductive analog-to-digital converter has attracted a lot of interests as one of the most prospective area of the application of Josephson Junction technology. One of the main advantages in using Rapid Single Flux Quantum logic in the analog-to-digital converter is the low voltage output from the Josephson junction switching, and hence the high resolution. To design an 1-bit analog-digital converter, first we have used XIC tool to compose a circuit schematic, and then studied the operational principle of the circuit with WRSPICE tool. Through this process, we obtained the proper circuit diagram of an 1-bit analog-digital converter circuit. Based on this circuit we performed margin calculations of the designed circuits and optimized circuit parameters. The optimized circuit was laid out as a mask drawing. Inductance values of the circuit layout were calculated with L-meter. Circuit inductors were adjusted according to these calculations and the final layout was obtained.

• 한국음향학회지
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• 제24권1호
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• pp.11-20
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• 2005

본 논문에서는 PLL (Phase Locked Loop)없이 동작할 수 있는 S/PDIF (Sony Philips Digital Interface) 수신기의 연구에 관하여 다룬다. 현재 대부분의 오디오 장치와 오디오 프로세서에서 S/PDIF 수신기가 사용되고 있음에도 불구하고, 국내에서는 이에 관한 연구가 많지 않은 실정이다. 현재 사용되고 있는 S/PDIF 수신용 상용 DAC(Digital-to-Analog Converters) 칩들은 모두 내부에 PLL 회로를 포함하고 있다. PLL 회로는 S/PDIF 디지틸 신호로부터 클럭 정보를 뽑아내고 클럭과 입력 신호간의 동기화를 맞추는 역할을 한다. 그러나, PLL 회로는 "아날로그 회로"라는 특성 때문에 VLSI (Very Large Scale Integrated Ciruits)회로의 SOCs (System On Chips)설계에 있어 많은 어려움을 야기한다. 본 논문에서는 PLL 회로 없이 순수 디지털 회로로만 구현된 S/PDIF 수신기를 제안하였다. 제안된 수신기의 핵심 아이디어는 16 MHz의 기본 클럭과 S/PDIF 신호의 속도비를 이용한다는 것이다. 본 논문에서는 수십만개의 S/PDIF 입력 신호에 대한 디코딩 확인 후, PLL같은 아날로그 회로 없이 순수 디지틸 회로만으로 S/PDIF 수신기를 설계할 수 있음을 확인하였다. 제안된 S/PDIF 수신기는 SOC 설계용 If로서 활용될 수 있을 것으로 본다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.377-380
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• 2000

In this paper, a new adaptive linearizer architecture with the predistorter is proposed. In the M.Ghaderi's paper, two analog predistorters and an envelope detector are used. Analog circuits for the analog predistorter and the envelope detector can cause imperfection and inaccuracy of the system and make circuits more complex. To solve those problems, most of processes including the predistortion are made by the DSP. The RLS algorithm is applied so that the errors between power amplifier output signals through the postdistorters and predistorted input signals can be converged to the global minimum.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.107.1-107
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• 2001

In this paper, a digital signal processing circuit for Position Sensitive Detectors(PSDs) is introduced to substitute the conventional analog signal processing circuit and to compensate disadvantages of the PSD. In general, the analog circuits have the problems such as noise accumulation, sensitivity for environmental changes, and high cost for manufacturing. Moreover, the intrinsic nonlinearity problem of the PSD makes it hard to measure the position accurately because it is difficult to be overcome the problem by using the conventional analog circuits, which can be solved by using the digital signal processing circuit. The circuit is implemented by using a Field Programmable Gate Array (FPGA). The Pulse Amplitude Modulation(PAM) method is used for reducing the environmental noise effect, and a linear interpolation logic is used to compensate the ...

• Journal of information and communication convergence engineering
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• 제14권4호
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• pp.268-271
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• 2016

An efficient inductive switching noise suppression technique for mixed-signal integrated circuits (ICs) using standard CMOS digital technology is proposed. The proposed design technique uses a parallel RC circuit, which provides a damping path for the switching noise. The proposed design technique is used for designing a mixed-signal circuit composed of a ring oscillator, a digital output buffer, and an analog noise sensor node for $0.13-{\mu}m$ CMOS digital IC technology. Simulation results show a 47% reduction in the on-chip inductive switching noise coupling from the noisy digital to the analog blocks in the same substrate without an additional propagation delay. The increased power consumption due to the damping resistor is only 67% of that of the conventional source damping technique. This design can be widely used for any kind of analog and high frequency digital mixed-signal circuits in CMOS technology

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2004년도 한국우주과학회보 제13권2호
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• pp.337-340
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• 2004

Upper stage telemetry system of KSLV- I (Korea Space Launch Vehicle I) is composed of MDU (Master Data Unit), RDU (Remote Data Unit), SRU (Shock Recorder Unit) and Transmitter. RDU is the front-end telemetry data acquisition unit which gathers analog/discrete signals from various sensors and other units, and transmits the processed data to MDU via MIL-STD-I553B data bus. In order to acquire useful data from analog signal, signal conditioning circuits, such as anti-aliasing or amplifying, should be implemented. For this purpose, SCM (Signal Conditioning Module) had been developed. This paper describes hardware structure of SCM and analog signal conditioning circuits for various sensors. Also, sampling time scheme for different sampling rates were designed and tested.