• Title/Summary/Keyword: Amplifier input transistor

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The Improvement of Matching of Amplifier Input Transistor for Display Driver IC (Display Driver IC용 Amplifier Input Transistor의 Matching 개선)

  • Kim, Hyeon-Cheol;Roh, Yong-Han
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.3
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    • pp.213-216
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    • 2008
  • The voltages for pixel electrodes on LCD panels are supplied with analog voltages from LCD Driver ICs (LDIs). The latest LDI developed for large LCD TV's has suffered from the degradation of analog output characteristics (target voltage: AVO and output voltage deviation: dVO). By the failure analysis, humps in $I_D-V_G$ curves have been observed in high voltage (HV) NMOS devices for input transistors in amplifiers. The hump is investigated to be the main cause of the deviation for the driving current in HV NMOS transistors. It also makes the matching between two input transistors worse and consequently aggravates the analog output characteristics. By simply modifying the active layout of HV NMOS transistors, this hump was removed and the analog characteristics (AVO &dVO) were improved significantly. In the help of the improved analog characteristics, it also became possible to reduce the size of the input transistors less than a half of conventional transistors and significantly improve the integration density of LDIs.

A Study on the Circuit Analysis of Composite BiCMOS Transistor and the Design Methodology of BiCMOS Differential Amplifier (복합 BiCMOS 트랜지스터의 회로 분석 및 그로 구성된 차동 증폭기의 설계기법에 관한 연구)

  • 송민규;김민규;박성진;김원찬
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.9
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    • pp.1359-1368
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    • 1989
  • In this paper, the composite BiCMOS transistor which combines a bipolar transistor and a MOS transistor in a cascade type, is analyzed in terms of I-V characteristics and small signal equivalent circuit. As a result, it has a larger driving capability than MOS transistor and a more extended rante of input voltage than bipolar transistor. Next, a BiCMOS differential amplifier as its application example is designed and compared with the CMOS one and the bipolar one. It increases the driving capability of the CMOS differential amp and improves the linear operation region of the bipolar differential amp.

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Efficiency Improvement of HBT Class E Power Amplifier by Tuning-out Input Capacitance

  • Kim, Ki-Young;Kim, Ji-Hoon;Park, Chul-Soon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.7 no.4
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    • pp.274-280
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    • 2007
  • This paper demonstrates an efficiency improvement of the class E power amplifier (PA) by tuning-out the input capacitance ($C_{IN}$) of the power HBT with a shunt inductance. In order to obtain high output power, the PA needs the large emitter size of a transistor. The larger the emitter size, the higher the parasitic capacitance. The parasitic $C_{IN}$ affects the distortion of the voltage signal at the base node and changes the duty cycle to decrease the PA's efficiency. Adopting the L-C resonance, we obtain a remarkable efficiency improvement of as much as 7%. This PA exhibits output power of 29 dBm and collector efficiency of 71% at 1.9 GHz.

Sense Amplifier Design for A NOR Type Non-Volatile Memory

  • Yang, Yil-Suk;Yu, Byoung-Gon;Roh, Tae-Moon;Koo, Jin-Gun;Kim, Jongdae
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1555-1557
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    • 2002
  • We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

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An analytical consideration of the MOS type field-effect transistor differential amplifier (MOS형 전계효과 트랜지스터 차동증폭기에 관한 소고)

  • 정만영
    • 전기의세계
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    • v.14 no.6
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    • pp.1-7
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    • 1965
  • This paper provides the analysis of the differential amplifier using the insulated gate, metala-oxide-semiconductor type field-effect-transistor(MOS FET), for its active element and the power drift of the amplifer. From these analytical considerations some design standardsn were found for the MOS FET differential amplifier available for the measurement of the very small current (pico-ampare range). A differential amplifier was designed and built in the view of above considerations. Its equivalent input gate voltages of the thermal drift and the power drift were 0.57mV/.deg. C in the range 25.deg. C-60.deg. C and 8.8mV/V in the range of 20% drift of its orginal value, respectively.

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Analysis of Transistorized Logarithmic Amplifier (트랜지스터 대수증폭기의 해석)

  • 이상배
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.6 no.1
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    • pp.19-22
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    • 1969
  • Detailed analysis has been developed concerning the transfer function and stability condition of the logarithmic amplifier using a common emitter transistor as a feed-back element. The analysis shows that input current vs output voltage transfer characteristics is accurately ogarithmic through entire operating current, and the time constant depends on input capcitance and collector-emitter equivalent resistance. Also the minimum value of imput capacitance required to stabilize the system is derived.

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Transistor Wide-Band Feedback Amplifiers (트랜지스터 광대역궤환증폭기)

  • 이병선;이상배
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.5 no.1
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    • pp.13-25
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    • 1968
  • A detailed analysis of the transistor wide-band feedback amplifiers using the hybrid-$\pi$ equivalent circuit has been made. It is considered both for the low freqnency and for the high frequency. The expressions of the gain, bandwidth. input impedance and output impedance have been presented. It is shown that a series feedback amplifier should be driven from the voltage source and should drive into the low resistance load, and a shunt feedback amplifier should be driven from the current source and should drive into the high resistance load. It is also shown that these stages can be coupled without use of the buffer stage or coupling transformer.

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Evaluation of GaN Transistors Having Two Different Gate-Lengths for Class-S PA Design

  • Park, Jun-Chul;Yoo, Chan-Sei;Kim, Dongsu;Lee, Woo-Sung;Yook, Jong-Gwan
    • Journal of electromagnetic engineering and science
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    • v.14 no.3
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    • pp.284-292
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    • 2014
  • This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

Slew-Rate Enhanced Low-Dropout Regulator by Dynamic Current Biasing

  • Jeong, Nam Hwi;Cho, Choon Sik
    • Journal of electromagnetic engineering and science
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    • v.14 no.4
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    • pp.376-381
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    • 2014
  • We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

Adjustable-Performace, Single-Ended Input Double-Balanced Mixer

  • Choi, Jin-Yong;Lee, Kyung-Ho;Lee, Sang-Gug
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.4
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    • pp.248-252
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    • 2001
  • A noble single-ended input, double-balanced mixer topology is proposed. The mixer incorporates the common-source amplifier input stage with inductive degeneration for impedance matching. The analysis based on simulations shows that the overall performance of the mixer is excellent and is adjustable by varying the input transistor size to give best characteristics for the given linearity specifications.

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