• Korean Journal of Optics and Photonics
• /
• v.23 no.4
• /
• pp.143-146
• /
• 2012

All-optical data extraction, one of the key technologies for all-optical computing and optical communication to perform add-drop, packet switching, and data reset, etc., is experimentally demonstrated by using cross-gain modulation (XGM) of semiconductor optical amplifiers (SOAs). Also, all-optical data extraction based on numerical simulation is performed by using the VPI simulation tool. In this paper, the suggested optical system based on SOAs shows the potential for high speed, and highly integrable and low power optical data computing.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.53 no.10
• /
• pp.510-514
• /
• 2004

In this paper, we analytically examine the voltage transfer function dependent on input conditions for an N-Input NAND Gate. The logic threshold voltage, defined as a voltage at which the input and the output voltage become equal, changes as the input condition changes for a static NAND Gate. The logic threshold voltage has the highest value when all the N-inputs undergo transitions and it has the lowest value when only the last input connected to the last NMOS to ground, makes a transition. This logic threshold voltage difference increases as the number of inputs increases. Therefore, in order to provide a near symmetric voltage transfer function, a multistage N-Input Gate consisting of 2-Input Logic Gates is desirable over a conventional N-Input Gate.

• Journal of Information Display
• /
• v.6 no.1
• /
• pp.17-21
• /
• 2005

We explored a new way of designing dynamic logic gates with low temperature polysilicon thin film transistors to increase the speed. The proposed architecture of logic gates utilizes the structural advantage of smaller junction capacitance of thin film transistors. This method effectively blocks leakage of current through the thin film transistors. Furthermore, the number of transistors used in logic gates is reduced thereby reducing power consumption and chip area. Through HSPICE .simulation, it is confirmed that the circuit speed is also improved in all logic gates designed.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.220-223
• /
• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• Proceedings of the Optical Society of Korea Conference
• /
• 2000.08a
• /
• pp.20-21
• /
• 2000

광을 기반으로 한 논리 연산은 전자 소자의 속도 한계 및 연산 용량의 한계를 극복할 대안으로 많은 관심을 끌고 있다. 초고속 전광 논리 연산의 구현은 대부분 물질의 비선형성을 이용하며 특히 광섬유의 비선형 Ken 효과를 이용한 Sagnac 간섭계의 형태를 이용한 논리 연산이 주로 연구되어 왔다$^{(1)}$ . 그러나 광섬유의 비선형성을 이용하기 위해서는 충분히 큰 광 강도가 필요하며 회로 구성에 있어서도 크기가 크다는 단점이 있다. 최근에는 반도체 광증폭기의 비선형 이득 포화 현상을 이용한 TOAD 등이 발표되어 상대적으로 크기도 감소하고 사용되는 광 강도 역시 감소시킬 수 있었다$^{(2)}$ . 간섭계를 이용한 광논리의 구현은 Sagnac 간섭계 뿐만 아니라 비선형 특성을 갖는 도파로로 구성된 Mach-Zehnder 간섭계, Michelson 간섭계 등도 이용이 가능하다. (중략)

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.52-58
• /
• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.3
• /
• pp.370-377
• /
• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

• Proceeding of EDISON Challenge
• /
• 2016.03a
• /
• pp.295-298
• /
• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• Proceedings of the Optical Society of Korea Conference
• /
• 2007.02a
• /
• pp.84-85
• /
• 2007

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.10
• /
• pp.1794-1800
• /
• 2008

This paper presents a method of constructing the digital logic switching functions using PLA. First of all, we propose a MIN and MAX algebra arithmetic operation based on the Post algebra. And we discuss the T-gate which is used for realization of the MIN and MAX algebra arithmetic operation. Next, we discuss the MIN array and MAX array which are basic circuit of the PLA, also we discuss the literal property. For the purpose of the design for the digital logic switching functions using PLA, we Propose the variable partition, modular structure design, literal generator, decoder and invertor. The proposed method is the more compactable and extensibility.