• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.2
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• pp.58-63
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• 2010

Cryptography is primarily a computationally intensive process. In this paper we expand AES scheme for analysis of computation time with four criteria, first is the compression of plain data, second is the variable size of block, third is the selectable round, fourth is the selective function of whole routine. We have tested our encryption scheme by c++ using MinGW GCC. Through extensive experimentations of our scheme we found that the optimal block size.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.97-99
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• 2005

정보보호 제품의 주요한 역할을 담당하는 암호 모듈의 구현 무결성을 보증하기 위해 많은 연구가 활발히 이루어지고 있다. 하지만 기존의 일반적인 테스팅 방법으로는 구현 무결성에 대해 신뢰하지 못한다. 본 논문에서는 NIST (the US National Institute of Science and Technology)에서 AES(Advanced Encryption Standard)로 제정된 Rijndael 블록암호 모듈을 Verilog로 구현하고 CBMC를 이용하여 새로운 방식의 구현 무결성 평가 방법을 제시하고자 한다.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.33-39
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• 2009

This paper presents a new secure scan design technique to protect secret key from scan-based side channel attack for an Advanced Encryption Standard(AES) core embedded on an System-on-a-Chip(SoC). Our proposed secure scan design technique can be applied to crypto IF core which is optimized for applications without the IP core modification. The IEEE1149.1 standard is kept, and low area and power consumption overheads and high fault coverage can be achieved compared to the existing methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.77-86
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• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• International Journal of Computer Science & Network Security
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• v.23 no.10
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• pp.129-134
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• 2023

The greatest challenge of this century is the protection of stored and transmitted data over the network. This paper provides a new hybrid algorithm designed based on combination algorithms, in the proposed algorithm combined with Hill and the Advanced Encryption Standard Algorithms, to increase the efficiency of color image encryption and increase the sensitivity of the key to protect the RGB image from Keyes attackers. The proposed algorithm has proven its efficiency in encryption of color images with high security and countering attacks. The strength and efficiency of combination the Hill Chipper and Advanced Encryption Standard Algorithms tested by statical analysis for RGB images histogram and correlation of RGB images before and after encryption using hill cipher and proposed algorithm and also analysis of the secret key and key space to protect the RGB image from Brute force attack. The result of combining Hill and Advanced Encryption Standard Algorithm achieved the ability to cope statistically

• Journal of Advanced Navigation Technology
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• v.23 no.5
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• pp.339-344
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• 2019

In order to prepare for the rise of data security threats caused by the information and communication technology, technology that can guarantee the stability of the data stored in the missile test set is important. For this purpose, encryption should be performed when data is stored so that it cannot be restored even if data is leaked, and integrity should be ensured even after decrypting the data. In this paper, we apply AES algorithm, which is a symmetric key cryptography system, to the missile test set, and Encrypt and decrypt according to the amount of data for each bit of each AES algorithm. We implemented the AES Rijndael algorithm in the existing inspection system to analyze the effect of encryption and apply the proposed encryption algorithm to the existing system. confirmation of suitability. analysis of capacity and Algorithm bits it is confirmed that the proposed algorithm will not affect the system operation and the optimal algorithm is derived. compared with the initial data, we can confirm that the algorithm can guarantee data undulation.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.207-213
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• 2019

Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.133-139
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• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• Archives of design research
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• v.17 no.1
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• pp.179-190
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• 2004

The human effort to make personal privacy and safety from outer environment has brought the improvement of security system through the technological development. Especially as a apartment dwelling and lifestyle is general, the role and function of door lock system is more important than ever. The research for user-centered approach and design on the door lock system should be implemented under the circumstances. This study has focused on the development of making safety as well as easy interface to design door lock system. The price also is competitive as compared with other door lock products. The goal of this study is to propose the alternatives not only to develop door lock design but also to search the innovative way of locking system design.