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http://dx.doi.org/10.12673/jant.2019.23.2.207

Design of Crypto-processor for Internet-of-Things Applications  

Ahn, Jae-uk (School of Electronics and Information Engineering, Korea Aerospace University)
Choi, Jae-Hyuk (School of Electronics and Information Engineering, Korea Aerospace University)
Ha, Ji-Ung (School of Electronics and Information Engineering, Korea Aerospace University)
Jung, Yongchul (School of Electronics and Information Engineering, Korea Aerospace University)
Jung, Yunho (School of Electronics and Information Engineering, Korea Aerospace University)
Publication Information
Journal of Advanced Navigation Technology / v.23, no.2, 2019 , pp. 207-213 More about this Journal
Abstract
Recently, the importance for internet of things (IoT) security has increased enormously and hardware-based compact chips are needed in IoT communication industries. In this paper, we propose low-complexity crypto-processor that unifies advanced encryption standard (AES), academy, research, institute, agency (ARIA), and CLEFIA protocols into one combined design. In the proposed crypto-processor, encryption and decryption processes are shared, and 128-bit round key generation process is combined. Moreover, the shared design has been minimized to be adapted in generic IoT devices and systems including lightweight IoT devices. The proposed crypto-processor was implemented in Verilog hardware description language (HDL) and synthesized to gate level circuit in 65nm CMOS process, which results in 11,080 gate counts. This demonstrates roughly 42% better than the aggregates of three algorithm implementations in the aspect of gate counts.
Keywords
Advanced encryption standard (AES); Academy; research; institute; agency (ARIA); CLEFIA; IoT; Low area;
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Times Cited By KSCI : 1  (Citation Analysis)
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