• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.336-340
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• 2007

This paper proposes a multicast scheme over IEEE 802.16 networks which support multiple upper layer protocols such as ATM, IPv4 packets, IPv6 packets, IEEE 802.3 over IPv4 and so on. The multicast capabilities over IEEE 802.16 are important both control plane and data plane. The proposed multicast scheme can be divided into two types: direct mapping and indirect mapping. The direct mapping scheme is that layer 3 address is directly mapped into CID information which is used for connection identifier at IEEE 802.16 link layer. The indirect mapping scheme has two steps for mapping between layer 3 address and layer 2 CID. Firstly, a layer 3 address translates to Ethernet MAC address with group MAC address. Secondly, a group MAC address is mapped into CID. The mapping scheme depends on the upper layer protocols.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.383-394
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• 2010

Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.15-27
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• 2003

Recently, the volume of data is increasing rapidly in server for multimedia service, according to development of multimedia application environment. In recent research for storage technology the technology like of the SAN(Storage Area Network) advantages in scalibility of storage devices, and can read data from multiple disk arrays through RAID 0, 5. The RAID 0 and 5 translate to logical address to physical address using equation, but in case of adding disks at the system with equation -based mapping, the problem that we must rearrange the whole data in the previous disks happens. We use the mapping table to solve this problem in recent, but we can not load the whole mapping table in main memory because it occupies too large space. Therefore the extra I/Os are demanded to evaluate real physical address of data, so total performance of the system is degraded. In this paper, we propose the mapping method that supports the scalibility in RAID 0 or 5 system. The proposing method applies small metadata, so- called SZIT and simple equation, so it is possible that we make translate logical address to physical address rapidly and it is scalable in disk extending simultaneously Our suggesting method, if we add disks to the striping system for expanding of storage capacity, has an advantage of never stop service. So, SZlT-based mapping method can do online-disk-expanding in real-time service.

• Journal of Internet Computing and Services
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• v.17 no.4
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• pp.27-34
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• 2016

The referents of internet addresses are no longer limited to web sites. A new address service by the international organization for the internet address (ICANN) introduces an open space for the TLD (Top Level Domain) strings so that each service, content, product, and other linguistic expressions may be allowed. The open TLD addresses are more suitable for representing the address of service units, contents, or products. In this paper, as an alternative to static Internet address service to return a consistent mapping result regardless of a user-specific different requirements, we design a dynamic internet address mapping model that returns mapping result to suit user particular requirements. In addition, we propose a method for implementing a internet address service without any changes in the existing domain protocols. It may implement a dynamic internet address by attaching to a encoded user's metadata and environment data within a internet address representation, and adding the module for dynamic mapping to the name servers. Through this proposal, trying to expand the functions of internet address, it is expected to be able to provide customized informaiton retrieval services for each user by using just internet address.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.488-493
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• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.142-150
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• 2021

Open-channel SSD is a new type of Solid-State Disk (SSD) that improves the garbage collection overhead and write amplification due to physical constraints of NAND flash memory by exposing the internal structure of the SSD to the host. However, the host-level Flash Translation Layer (FTL) provided for open-channel SSDs in the current Linux kernel consumes host memory excessively because it use page-level mapping table to translate logical address to physical address. Therefore, in this paper, we implemente a selective mapping table loading scheme that loads only a currently required part of the mapping table to the mapping table cache from SSD instead of entire mapping table. In addition, to increase the hit ratio of the mapping table cache, filesystem information and mapping table access history are utilized for cache replacement policy. The proposed scheme is implemented in the host-level FTL of the Linux kernel and evaluated using open-channel SSD emulator. According to the evaluation results, we can achieve 80% of I/O performance using the only 32% of memory usage compared to the previous host-level FTL.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1307-1316
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• 1996

In this paper, we propose a vector quantization method which uses a dynamic address mapping based on exploring the high interblock correlation. In the proposed method, we reduce bit-rate by defining an address transform function, which maps a VQ address of an input block which will be encoded into a new address in the reordered codebook by using side match error. In one case that an original address can be transformed into a new transformed address which is lower than the threshold value, we encode the new address of the transformed convector, and in the other case we encode the address of the original convector which is not transformed. Experimental results indicate that the proposed scheme reduces the bit-rate by 45~50% compared with the ordi-nary VQ method forimage compression, at the same quality of the reconstructed image as that of the ordinary VQ system.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.