The KIPS Transactions:PartD (정보처리학회논문지D)

Korea Information Processing Society (한국정보처리학회)
권호 표지
DOI QR코드

DOI QR Code

HAMM(Hybrid Address Mapping Method) for Increasing Logical Address Mapping Performance on Flash Translation Layer of SSD

SSD 플래시 변환 계층 상에서 논리 주소 매핑의 성능 향상을 위한 HAMM(Hybrid Address Mapping Method)

  • 이지원 (연세대학교 컴퓨터과학과) ;
  • 노홍찬 (연세대학교 컴퓨터과학과) ;
  • 박상현 (연세대학교 컴퓨터과학과)
  • Received : 2010.04.06
  • Accepted : 2010.07.06
  • Published : 2010.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

최근 플래시 메모리 기반 SSD(Solid State Disks)는 데이터 처리 속도가 빠르고, 외부 충격에 강하며 전력소모가 작다는 우수한 특성과 함께 그 용량의 증가와 가격 하락으로 인하여 차세대 저장 매체로 부각되고 있다. 하지만 SSD는 하드디스크와는 달리 읽기, 쓰기 및 지우기의 단위 및 수행 시간이 다르며 덮어쓰기가 불가능하다는 특징이 있다. 이 때문에 SSD는 기존의 하드디스크 기반 시스템 상에서는 그 동작의 효율성이 떨어지며, 이를 보완하기 위해 플래시 변환 계층이 설계되었다. 본 논문에서는 플래시 변환 계층의 역할 중 하나인 논리 주소 매핑 기법을 개선하여 SSD의 성능을 높일 수 있는 HAMM(Hybrid Address Mapping Method)를 제안한다. HAMM은 기존에 존재하는 슈퍼 블록 매핑 기법과 블록 매핑 기법의 단점을 보완하고 장점을 살릴 수 있도록 설계된 논리 주소 매핑 기법이다. SSD 시뮬레이터를 제작하여 실험하였으며, 실험을 통하여 HAMM은 같은 크기의 쓰기 버퍼 상에서 슈퍼 블록 매핑 기법에 비해 SSD의 저장공간을 효율적으로 사용하는 것으로 나타났으며, 또한 블록 매핑 기법에 비해 매핑 테이블을 구성하는데 적은 양의 메모리를 사용하면서 비슷한 성능을 보이는 것으로 나타났다.

Keywords

References

  1. Jeong-Uk Kang, Heeseung Jo, Jin-Soo Kim and Joonwon Lee, “A Superblock-based Flash Translation Layer for NAND Flash Memory”, Proceedings of the 6th ACM & IEEE International conference on Embedded software, pp.161-170, 2006.
  2. Jesung Kim, Jongmin Kim, Sam H. Noh, SangLyul Min and Yookun Cho, “A Space-Efficient Flash Translation Layer for Compactflash Systems”, IEEE Transactions on Consumer Electronics, Vol.48, No.2, pp.366-375, 2002. https://doi.org/10.1109/TCE.2002.1010143
  3. Young-Hyun Bae, “Design of A High Performance Flash Memory-based Solid State Disk”, KIISE, Vol.25, No.6, pp. 18-28, 2007.
  4. Jim Gray, Bob Fitzgerald, “Flash Disk Opportunity for Server Applications”, ACM Queue, Vol.6, No.4, pp 18-23, 2008. https://doi.org/10.1145/1413254.1413261
  5. Goetz Graefe, Hewlett-Packard Laboratories, “The Five-Minute Rule 20 Years Later: and How Flash Memory Changes the Rules”, ACM QUEUE, Vol.6, Issue 4, pp.40-52, 2008. https://doi.org/10.1145/1413254.1413264
  6. Sangwon Lee, Dongjoo Park, Teasun Chung, Dongho Lee, Sangwon Park and Hajoo Song, “A Log Buffer-Based Flash Translation Layer Using Fully Associative Sector Translation,” ACM Transactions on Embedded Computer Systems, Vol.6, No.3, Article No. 18, 2007.
  7. Intel Corporation, “Understanding the Flash Translation Layer(FTL) Specification”, Dec. 1998.
  8. Amir Ban, “FLASH FILE SYSTEM”, USPTO.5404485, 1995.
  9. Aayush Gupta, Youngjae Kim and Bhuvan Urgaonkar, “DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings”, Proceeding of the 14th international conference on Architectural support for programming languages and operating systems, pp.229-240, 2009.
  10. http://www.todaysppc.com/mbzine/bbs/zboard.php?id=TipsNManuals&page=1&sn1=&divpage=1&sn=off&ss=on&sc=on&select_arrange=headnum&desc=asc&no=44
  11. Eran Gal et al., “Algorithms and Data Structures for Flash Memories”, Vol.37, No.2, pp.138-163, 2005. https://doi.org/10.1145/1089733.1089735
  12. Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy, “Design tradeoffs for SSD performance”, In USENIX Annual Technical Conference, 2008.
  13. Jeong-Woo Lee, Dong-Ryul Ryu, “SEMICONDUCTOR SOLID STATE DISK CONTROLLER”, USPTO. 20070106836, 2007.
  14. Jiwon Lee, Hongchan Roh, Sanghyun Park, “Dual Address Mapping Method for Efficient Wear-Leveling of SSDs”, Proceedings of 1st International Conference on Emerging Databases(EDB2009), pp.29-33, August, 2009.
  15. W. W. Hsu, A. J. Smith, and H. C. Young, “I/O reference behavior of production database workloads and the TPC benchmarks - an analysis at the logical level” Technical Report CSD-99-1071, Computer Science Division, University of California, Berkeley, Nov. 1999.
  16. http://technet.microsoft.com/en-us/sysinternals/bb896646.aspx
  17. http://sourceforge.net/projects/benchmarksql/