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An Address Translation Technique Large NAND Flash Memory using Page Level Mapping  

Seo, Hyun-Min (서울대학교 컴퓨터공학부)
Kwon, Oh-Hoon (서울대학교 컴퓨터공학부)
Park, Jun-Seok (서울대학교 컴퓨터공학부)
Koh, Kern (서울대학교 컴퓨터공학부)
Publication Information
Journal of KIISE:Computing Practices and Letters / v.16, no.3, 2010 , pp. 371-375 More about this Journal
Abstract
SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.
Keywords
FTL; SSD; NAND Flash; Address Translation;
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1 D. Lee, J. Choi, J.-H. Kim, S.H. Noh, S.L. Min, Y. Cho, and C.S. Kim, "LRFU: A Spectrum of Policies that Subsumes the Least Recently Used and Least Frequently Used Policies," IEEE Trans. Computers, vol.50, no.12, pp.1352-1360, Dec. 2001.   DOI   ScienceOn
2 S. Lee, D. Shin, Y. Kim, and J. Kim, "LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems," In Proceedings of the International Workshop on Storage and I/O Virtualization, Performance, Energy, Evaluation and Dependability (SPEED2008), Feburary 2008.
3 M.-L. Chiang, P. C. H. Lee, and R.-C. Chang, "Using data clustering to improve cleaning performance for flash memory," Software: Practice and Experience, vol.29, no.3, pp.267-290, 1999.   DOI   ScienceOn
4 E.J. O'Neil, P.E. O'Neil, and G. Weikum, "The LRU-K Page Replacement Algorithm for Database Disk Buffering," Proc. ACM Int'l Conf. Management of Data (Sigmod '93), May 1993.
5 Micron MLC NAND (MT29F64G08UAAC4) datasheet http://www.micron.com.
6 J. Kim, J. M. Kim, S. Noh, S. L. Min, and Y. Cho, "A space-efficient flash translation layer for compactflash systems," Consumer Electronics, IEEE Transactions on, vol.48, no.2, pp.366-375, May 2002.   DOI   ScienceOn
7 J. Kang, H. Jo, J. Kim, and J. Lee, "A Superblock- based Flash Translation Layer for NAND Flash Memory," In Proceedings of the International Conference on Embedded Software (EMSOFT), pp.161-170, October 2006. ISBN 1-59593- 542-8.
8 T. Chung, D. Park, S. Park, D. Lee, S. Lee, and H. Song, "System Software for Flash Memory: A Survey," In Proceedings of the International Conference on Embedded and Ubiquitous Computing, pp.394-404, August 2006.
9 S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song, "A log buffer-based flash translation layer using fully-associative sector translation," Trans. on Embedded Computing Sys., vol.6, no.3, pp.18, 2007.   DOI