1 |
S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, and H. J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Transactions on Embedded Computing Systems, Vol.6, No.3, Article 18, 2007.
|
2 |
J. U. Kang, H. Jo, J. S. Kim, and J. Lee "A Superbloc k-based Flash Translation Layer for NAND Flash Memory" Proc. of EMSOFT, pp 161-170, 2006.
|
3 |
http://www.futuremark.com/products/pcmark05/
|
4 |
S. H. Park, J. W. Park, J. M. Jeong, J. H. Kim, and S. D. Kim, "A Mixed Flash Translation Layer Structure for SLC-MLC Combined Flash Memory System", Proc of IEEE Workshop on Storage and I/O Virt ualization, Performance, Energy, Evaluation and Dependability 2008.
|
5 |
T. Shinohara, "Flash Memory Card with Block Mem ory Address Arrangement," United States Patent, No. 5,905,993, 1999.
|
6 |
J. W. Park, S. H. Park, G. H. Park, and S. D. Kim, "An integrated mapping table for hybrid FTL wㅑth fault-tolerant address cache", IEICE Electronics Express, Vol.6 No.7, pp368-374, April, 2009.
DOI
|
7 |
Understanding the Flash Translation Layer (FTL) Specification, Intel Corporation, 1998.
|
8 |
E. Harari, R. D. Norman, and S. Mehrotra, "Flash EEPROM System", US Patent, No. 5,602,987, Dec. 1993.
|
9 |
A. Ban, "Flash File System Optimized for Page-mode Flash Technologies", US Patent, No. 5,937,425, Oct. 1997.
|
10 |
A. Ban, "Flash File System", U. S. Patent 5,404,485, 1995.
|
11 |
J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, "A Space-Efficient Flash Translation Layer for Compact Flash System," IEEE Transactions on Consumer Electronics, Vol.48, No.2, pp. 366-375, 2002.
DOI
ScienceOn
|