Browse > Article

An Efficient Address Mapping Table Management Scheme for NAND Flash Memory File System Exploiting Page Address Cache  

Kim, Cheong-Ghil (남서울대학교 컴퓨터학과)
Publication Information
Journal of Digital Contents Society / v.11, no.1, 2010 , pp. 91-97 More about this Journal
Abstract
Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.
Keywords
NAND flash memory; file translation layer; hybrid address mapping; cache;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park, and H. J. Song, "A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation," ACM Transactions on Embedded Computing Systems, Vol.6, No.3, Article 18, 2007.
2 J. U. Kang, H. Jo, J. S. Kim, and J. Lee "A Superbloc k-based Flash Translation Layer for NAND Flash Memory" Proc. of EMSOFT, pp 161-170, 2006.
3 http://www.futuremark.com/products/pcmark05/
4 S. H. Park, J. W. Park, J. M. Jeong, J. H. Kim, and S. D. Kim, "A Mixed Flash Translation Layer Structure for SLC-MLC Combined Flash Memory System", Proc of IEEE Workshop on Storage and I/O Virt ualization, Performance, Energy, Evaluation and Dependability 2008.
5 T. Shinohara, "Flash Memory Card with Block Mem ory Address Arrangement," United States Patent, No. 5,905,993, 1999.
6 J. W. Park, S. H. Park, G. H. Park, and S. D. Kim, "An integrated mapping table for hybrid FTL wㅑth fault-tolerant address cache", IEICE Electronics Express, Vol.6 No.7, pp368-374, April, 2009.   DOI
7 Understanding the Flash Translation Layer (FTL) Specification, Intel Corporation, 1998.
8 E. Harari, R. D. Norman, and S. Mehrotra, "Flash EEPROM System", US Patent, No. 5,602,987, Dec. 1993.
9 A. Ban, "Flash File System Optimized for Page-mode Flash Technologies", US Patent, No. 5,937,425, Oct. 1997.
10 A. Ban, "Flash File System", U. S. Patent 5,404,485, 1995.
11 J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, "A Space-Efficient Flash Translation Layer for Compact Flash System," IEEE Transactions on Consumer Electronics, Vol.48, No.2, pp. 366-375, 2002.   DOI   ScienceOn