• Journal of Power Electronics
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• v.18 no.3
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• pp.662-671
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• 2018

This paper presents a new structure for a step up dc-dc converter, which has several advantageous features. Firstly, the input dc source and the clamped capacitor are connected in series to transfer energy to the load through dual voltage multiplier cells. Therefore, the proposed converter can produce a very high voltage and a high conversion efficiency. Secondly, a double voltage clamped circuit is introduced to the primary side of the coupled inductor. The energy of the leakage inductance of the coupled inductor is recycled and the inrush current problem of the clamped circuits can be shared equally by two synchronous clamped capacitors. Therefore, the voltage spike of the switch tube is solved and the current stress of the diode is reduced. Thirdly, dual voltage multiplier cells can absorb the leakage inductance energy of the secondary side of the coupled inductor to obtain a higher efficiency. Fourthly, the active switch turns on at almost zero current and the reverse-recovery problem of the diodes is alleviated due to the leakage inductance, which further improves the conversion efficiency. The operating principles and a steady-state analysis of the continuous, discontinuous and boundary conduction modes are discussed in detail. Finally, the validity of this topology is confirmed by experimental results.

• ETRI Journal
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• v.33 no.3
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1650-1660
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• 2016

This paper proposes a compensator to eliminate the DC bias of inductor current. This method utilizes an average-current sensing technique to detect the DC bias of inductor current. A small signal model of the DC bias compensation loop is derived. It is shown that the DC bias has a one-pole relationship with the duty cycle of the left side leading lag. By considering the pole produced by the dual active bridge (DAB) converter and the pole produced by the average-current sensing module, a one-pole-one-zero digital compensation method is given. By using this method, the DC bias is eliminated, and the stability of the compensation loop is ensured. The performance of the proposed compensator is verified with a 1.2-kW DAB converter prototype.

• Journal of Power Electronics
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• v.13 no.4
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• pp.636-646
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• 2013

A single-phase tapped-inductor boost converter has been proposed previously. However, detailed characterization and performance analysis were not conducted. This paper presents a detailed characterization, performance analysis, and design expressions of a single-phase tapped-coupled-inductor boost converter. Expressions are derived for average and RMS input current as well as for RMS input and output capacitor current ripple. A systematic approach for sizing the tapped-coupled inductor, active switch, and output diode is presented; such approach has not been reported in related literature. This study reveals that sizing of the inductor has to be based on current ripple requirement, turns ratio, and load. Conditions that produce discontinuous inductor current are also discussed. Analysis of a non-ideal converter operating in continuous conduction mode is also conducted. The expression for the voltage ratio considering the coupling coefficient is derived. The suitability of the converter for high-voltage step-up applications is evaluated. Factors that affect the voltage boost ratio are also identified. The effects of duty ratio and load variation on the performance of the converter are also investigated. The theoretically derived characteristics are validated through simulations. Experimental results obtained at a low power level are included to validate the analytical and simulation results. A good agreement is observed among the analytical, simulation, and experimental results.

• Journal of Power Electronics
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• v.13 no.3
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• pp.479-486
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• 2013

This paper presents a control strategy for distributed systems, which can be used in islanded microgrids. The control strategy is based on the droop method, which uses locally measured feedback to achieve load current sharing. Instead of the traditional droop method, an improved one is implemented. A virtual inductor in the synchronous frame for three-phase inverters is proposed to deal with the coupling of the frequency and the amplitude related to the active and reactive power. Compared with the traditional virtual inductor, the proposed virtual inductor is not affected by high frequency noises because it avoids differential calculations. A model is given for the distributed generation system, which is beneficial for the design of the droop coefficients and the value of the virtual inductor. The effectiveness of the proposed control strategy is verified by simulation and experiment results.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.485-486
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• 2019

본 논문에서는 정격부하에서 효율이 가장 높으면서 동시에 Zero Voltage Switching(ZVS)를 만족하는 인덕터를 설계하는 방법을 제안한다. 제안하는 인덕터 설계 방법은 주어진 정격에서 스위치에 존재하는 스너버 캐패시터를 고려한 ZVS 식을 구하며, 스위치의 특성을 고려한 Dead-time을 설계하고 이를 통해 인덕턴스를 최소화 한다. 시뮬레이션을 통해 스너버 캐패시터의 전압 파형 및 스위치의 손실을 비교하였다.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• Journal of Power Electronics
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• v.17 no.3
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• pp.579-589
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• 2017

In this study a new high step-up dc-dc converter is presented. The operation of the proposed converter is based on the capacitor switching and coupled inductor with a single active power switch in its structure. A passive voltage clamp circuit with two capacitors and two diodes is used in the proposed converter for elevating the converter's voltage gain with the recovered energy of the leakage inductor, and for lowering the voltage stress on the power switch. A switch with a low $R_{DS}$ (on) can be adopted to reduce conduction losses. In the generalized mode of the proposed converter, to reach a desired voltage gain, capacitor stages with parallel charge and series discharge techniques are extended from both sides of secondary side of the coupled inductor. The proposed converter has the ability to alleviate the reverse recovery problem of diodes with circuit parameters. The operating principle and steady-states analyses are discussed in detail. A 40W prototype of the proposed converter is implemented in the laboratory to verify its operation.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.88-93
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• 2016

LCL filters are widely used in high-order harmonics attenuation of output currents in grid-connected inverters. However, output currents of grid-connected inverters with LCL filters can become unstable because of the resonance of the filters. Given that the characteristics of output currents in inverters mostly depend on filter performance, the exact analysis of filters by considering parasitic components is necessary for both harmonics attenuation and current control. LCL filters have three or four parasitic components: the series and/or parallel resistance of the filter capacitor and the series resistance of the two filter inductors. Most studies on LCL filters have focused on the parasitic components of the filter capacitor. Although several studies have addressed the parasitic components of the filter inductor at the inverter side, no study has yet investigated the concurrent effects of series resistance in both filter inductors in detail. This paper analyzes LCL filters by considering series resistance in both filter inductors; it proposes an active damping method based on the virtual series resistance of LCL filters. The performance of the proposed active damping is then verified through both simulation and experiment using Hardware-in-the-Loop Simulator(HILS).

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.150-158
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• 2017

This study proposes a new pulse-width modulation switching pattern for the low conduction loss of a three-level neutral point clamped (NPC)-based dual-active bridge (DAB) converter. The operational principle for a bidirectional power conversion is a phase-shift modulation. The conventional switching method of the three-level NPC-based DAB converter shows a symmetric switching pattern. This method has a disadvantage of high root-mean-square (RMS) value of the coupling inductor current, which leads to high conduction loss. The proposed switching method shows an asymmetrical pattern, which can reduce the RMS value of the inductor current with lower conduction loss than that of the conventional method. The performance of the proposed asymmetrical switching method is theoretically analyzed and practically verified using simulation and experiment.