• Proceedings of the KSME Conference
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• 2001.06e
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• pp.213-218
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• 2001

The characteristics of the fluid flow and mass transfer in a vertical atmospheric pressure chemical vapor deposition (APCVD) are numerically studied. In order to get the optimal process parameters for the uniformity of deposition on a substrate, Navier-Stokes and energy equations have been solved for the pressure, mass-flow rate and temperature distribution in a CVD reactor. Results show that the thermal boundary condition at the reactor wall has an important effect in the formation of buoyancy-driven secondary cell when radiation effect is considered. Results also show that reduction of the buoyancy effect on the heated reactor improves the uniformity of deposition.

• Journal of Sensor Science and Technology
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• v.19 no.1
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• pp.31-35
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• 2010

High temperature micro pressure sensors were fabricated by using polycrystalline 3C-SiC piezoresistors grown on oxidized SOI substrates by APCVD. These have been made by bulk micromachining under $1{\times}1mm^2$ diaphragm and Si membrane thickness of $20{\mu}m$. The pressure sensitivity of implemented pressure sensors was 0.1 mV/$V{\cdot}bar$. The nonlinearity and the hysteresis of sensors were ${\pm}0.44%{\cdot}FS$ and $0.61%{\cdot}FS$. In the temperature range of $25^{\circ}C{\sim}400^{\circ}C$ with 5 bar FS, TCS (temperature coefficient of sensitivity), TCR (temperature coefficient of resistance), and TCGF (temperature coefficient of gauge factor) of the sensor were -1867 ppm/$^{\circ}C$, -792 ppm/$^{\circ}C$, and -1042 ppm/$^{\circ}C$, respectively.

• Journal of Sensor Science and Technology
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• v.22 no.3
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• pp.175-180
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• 2013

This paper describes the characteristics of cubic silicon carbide (3C-SiC) films grown on a carbonized Si(100) substrate, using hexamethyldisilane (HMDS, $Si_2(CH_3)_6$) as a safe organosilane single precursor in a nonflammable $H_2$/Ar ($H_2$ in Ar) mixture carrier gas by atmospheric pressure chemical vapor deposition (APCVD) at $1280^{\circ}C$. The growth process was performed under various conditions to determine the optimized growth and carbonization condition. Under the optimized condition, grown film has a single crystalline 3C-SiC with well crystallinity, small voids, low residual stress, low carrier concentration, and low RMS. Therefore, the 3C-SiC film on the carbonized Si (100) substrate is suitable to power device and MEMS fields.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.171-173
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• 1991

the poly silicon film was deposited by APCVD. and then the deposition mechanism and electrical characteristics was investigated for that film. The grain phase, the deposition rate, and the etch characteristics were evaluated according to the deposition conditions. The criteria temperature of surface morphology state was $730^{\circ}C {\sim}780^{\circ}C$ between the mirror phase grain and the powder phase grain.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.169-169
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• 2003

실리콘 절연막은 반도체 및 디스플레이 소자의 gate 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는데, 주로 IPCVD, PECVD, APCVD법에 의하여 증착되고 있다. 그러나 이러한 방법들은 반도체 소자의 고집적화가 진행됨에 따라 증착온도와 step coverage 및 물성 이 문제점으로 대두되고 있다. 이러한 문제점들을 해결할 수 있는 원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 우수한 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 또 저온에서 증착이 가능해 유리를 기판으로 사용하는 TFT-LCD소자의 gate 절연막에 적용이 가능하다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1351_1352
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• 2009

We deposited $SnO_2$:F thin films by atomospheric pressure chemical vapor deposition(APCVD) on corning glass. $SnO_2$:F films were used as transparent conductive oxide (TCO) electrode for Si thin film solar cells. We have investigated structural, electrical and optical properties of $SnO_2$:F thin films and fabricated thin film Si solar cells by plasma enhanced CVD(PECVD) on $SnO_2$:F thin films The cells were characterized by I-V measurement using AM1.5 spectra. Conversion efficiency of our cells were between 5.61% and 6.45%.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.179-182
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• 2007

Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.183-187
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• 2007

The magnetron reactive ion etching (RIE) characteristics of polycrystalline (poly) 3C-SiC grown on $SiO_2$/Si substrate by APCVD were investigated. Poly 3C-SiC was etched by $CHF_3$ gas, which can form a polymer as a function of side wall protective layers, with additive $O_2$ and Ar gases. Especially, it was performed in magnetron RIE, which can etch SiC at lower ion energy than a commercial RIE system. Stable etching was achieved at 70 W and the poly 3C-SiC was undamaged. The etch rate could be controlled from $20\;{\AA}/min$ to $400\;{\AA}/min$ by the manipulation of gas flow rates, chamber pressure, RF power, and electrode gap. The best vertical structure was improved by the addition of 40 % $O_2$ and 16 % Ar with the $CHF_3$ reactive gas. Therefore, poly 3C-SiC etched by magnetron RIE can expect to be applied to M/NEMS applications.