• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2317-2325
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• 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.352-353
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• 2013

본 연구에서는 12bit 1MSps 연속 근사화 아날로그-디지털 변환기(Analog to Digital Converter : ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 0.18um 1Metal 6Poly CMOS 공정을 이용하였고, Cadence tool을 이용하여 시뮬레이션 및 레이아웃 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 6mW였고, 입력 신호의 주파수가 100kHz 일 때, SNDR은 69.53dB, 유효 비트수는 11.26bit의 결과를 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.293-294
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• 2014

본 논문에서는 MOS 커패시터를 이용하여 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 매그나칩/SK하이닉스 $0.18{\mu}m$ 공정을 이용하였으며, Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 3.22mW였고, 유효 비트수는 11.5bit의 결과를 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of Plant Biology
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• v.39 no.2
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• pp.107-112
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• 1996

To study the compensatory aspect of putrescine biosynthetic enzyme n tobacco suspension cultured cells, we examined the contents of the cellular polyamines and the activities of arginine decarboxylase (ADC, EC 4.1.1.19) and ornithine decarboxylase (ODC, EC 4.1.1.17) in the tobacco suspension cells treated with $\alpha$-difluoromethyl arginine (DFMA) or $\alpha$-difluoromethyl ornithine (DFMO). In the untreated cells, the content of the cellular putrescine was decreased during the first 3 hours and then subsequently increased. However, the content of the cellular spermidine and spermine remained constant during the incubation time. While ADC activity increased after 6 hours, ODC activity decreased following the rapid increase until 6 hours. DFMA induced the decrease in the contents of putrescine and spermidine, and the increase in that of spermine. It also caused the inhibition of ADC and ODC activities throughout the incubation time. DFMO produced the stimulation of ADC activity about 2 times of untreated cells and the decrease in the content of putrescine about 50% of them at 12 hour. The application of putrescine or cycloheximide prevented the increase of ADC activity by DFMO but that of actinomycin-D did not show any detectable effect. The stimulation of ADC activity by DFMO in tobacco suspension cultured cells was probably due to the enhancement of de novo synthesis for ADC protein, which might be regulated in the translation step by the content of the cellular putrescine.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• Journal of Chest Surgery
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• v.37 no.12
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• pp.967-977
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• 2004

Background: DNA methylation is one of the important gene expression mechanisms of the cell. When cytosine of CpG dinucleotide in promotor is hypomethylated, expression of some genes that is controlled by this promoter is altered. In this study, the author investigated the effect of DNA demethylating agent, 5-aza-2'-deoxycytidine (ADC), on the expressions of cancer antigen genes, MHC and B7 in 4 lung cancer cell lines, NCIH1703, NCIH522, MRC-5, and A549. Material and Method: After treatment of cell lines, NCIH1703, NCIH522, MRC-5 and A549 with ADC (1 uM) for 48 hours, RT-PCR was performed by using the primers of MAGE, GAGE, NY-ESO-1, PSMA, CEA, and SCC antigen gene. In order to find the optimal ADC treatment condition for induction of cancer antigen, we studied the effect of ADC treatment time and dose on the cancer antigen gene expression. To know the effect of ADC on the expression of MHC or B7 and cell growth, cells were treated with 1 uM of ADC for 72 hours for FACS analysis or cells were treated with 0.2, 1 or 5 uM of ADC for 96 hours for cell counting. Result: After treatment of ADC (1 uM) for 48 hours, the expressions of MAGE, GAGE, NY-ESO-1, and PSMA genes increased in some cell lines. Among 6 MAGE isotypes tested, and gene expression of MAGE-1, -2, -3, -4 and -6 could be induced by ADC treatment. However, CEA gene expression did not change and SCC gene expression was decreased by ADC treatment. Gene expression was generally induced 24 - 28 hours after ADC treatment and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC ADC teatment, and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC teatment in ADC-Free medium. Most gene expression could be induced at 0.2 uM of ADC, but gene expression increased dependently on ADC treatment dose. The expression of MHC and B7 was not increased by ADC treatment in all four cell lines, and the growth rate of 4 cell lines decreased significantly with the increase of ADC concentrations. Conclusion: Treatment of lung cancer cell lines with ADC increases the gene expression MAGE, GAGE and NY-ESO-1 that are capable of induction of cytotoxic T lymphocyte response. We suggest that treatment with 1 uM of ADC for 48 hours and then culturing in ADC-free medium is optimal condition for induction of cancer antigen. However, ADC has no effect on MHC and B7 induction, additional modification for increase of expression of MHC, B7 and cytokine will be needed for production of efficient cancer cell vaccine.