• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.4
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• pp.545-552
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• 2011

In this article, reference voltages in a general flash ADC are not obtained from a series of resistors but floating gates. When a behavior model simulation was performed in a pipelined ADC including the suggested flash ADC as a result of an ADC's overall function, it showed results that SNR is approximately 77 dB and resolution is 12 bit. And more than almost 90% showed INL within ${\pm}0.5$ LSB, and like INL, more than 90% showed DNL within ${\pm}0.5$ LSB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.7
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• pp.623-629
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• 2013

This paper presents the implementation result of the EEG(electroencephalogram) signal transmission protocol and its test platform. EEG measured by a dry-type electrode is directly converted into digital signal by ADC(analog-to-digital converter). Thereafter it is transferred DSP(digital signal processor) platform by $I^2C$(inter-integrated circuit) protocol. DSP conducts the pre-processing of EEG and extracts feature vectors of EEG. In this work, we implement the $I^2C$ protocol with 16 channels by using 10 or 12-bit ADC. In the implementation results, the overhead ratio for the 4 bytes data burst transmission measures 2.16 and the total data rates are 345.6 kbps and 414.72 kbps with 10-bit and 12-bit 1 ksps ADC, respectively. Therefore, in order to support a high speed mode of $I^2C$ for 400 kbps, it is required to use 16:1 and $(8:1){\times}2$ ratios for slave:master in 10-bit ADC and 12-bit ADC, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.295-301
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• 2012

In this article, we have designed SHA, which has 12 Bit resolution at an input signal range of 1 $V_{pp}$ and operates at a sampling speed of 100 MS/s in order to use at front of high speed ADC. SFDR(Spurious Free Dynamic Range) of the proposed system drops to approximately 66.3 dB resolution when the input frequency is 5 MHz, and the sampling frequency is 100 MHz, however, the circuit without a feedthrough has 12 bit resolution with approximately 73 dB.

• Journal of Korea Foundry Society
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• v.32 no.3
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• pp.157-164
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• 2012

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of Radiation Protection and Research
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• v.12 no.1
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• pp.12-25
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• 1987

A basic multichannel analyser (MCA) system have been designed and constructed with the successive approximation type ADC (Analog to Digital Converter). Linear Gate, window, and palse stretcher consist of mainly linear and logic IC's, and are properly combined together to achieve short dead time and good linearity of the system. ADC 1211 (analysing time: $120{\mu}sec$) and S-RAM (static random acess memory) 6264 are used in ADC module. Two 6264 memories are connected in parallel in order to-provide enough counting capacity ($2^{16}-1$). Interfaced microcomputer Apple II controls this system and analizes the counted data. The system is tested by input pulses between 0V to 10V from oscillator.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• Journal of the Korean Society of Radiology
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• v.12 no.6
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• pp.755-762
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• 2018

The purpose of this study was to compare the FA(faractional anisotropy) and ADC(apparent diffusion coefficient) values, which were derived from diffusion tensor imaging in breast cancer patients. The diffusion gradient used in this study was derived from quantitative diffusion indices using 20 directions(b-value, 0 and $1,000s/mm^2$). Quantitative analysis was analyzed using Pearson's correction and qualitative analysis using for correction coefficients. As a result, $FA_{min}$, $FA_{mean}$ and $FA_{max}$ were $0.098{\pm}0.065$, $0.302{\pm}0.142$ and $0.634{\pm}0.236$, respectively(p > 0.05). The $ADC_{min}$, $ADC_{mean}$ and $ADC_{max}$ were $0.741{\pm}0.403$, $1.095{\pm}0.394$ and $1.530{\pm}0.447$, respectively(p > 0.05). The $FA_{min}$, $FA_{mean}$, and $FA_{max}$ mean values were $0.132{\pm}0.050$, $0.418{\pm}0.094$, and $0.770{\pm}0.164$ for Category 6 and Kinetic Curve Pattern III, respectively. $ADC_{min}$, $ADC_{mean}$, and $ADC_{max}$ were $0.753{\pm}0.189$, $1.120{\pm}0.236$, and $1.615{\pm}0.372$, respectively. Quantitative analysis showed negative correlation between $ADC_{mean}-FA_{mean}$ and $ADC_{max}-FA_{max}$(p = 0.001, 0.003). The qalitative analysis showed ADC 0.628(p = 0.001), FA 0.620(p = 0.001) in the internal evaluations, ADC 0.677(p = 0.001), FA 0.695(p = 0.001) in external evaluations. In conclusion, based on the morphological examination, time to signal intensity graph is the form of wash-out(pattern III) in the dynamic contrast enhance examination, As a result, the $ADC_{mean}$ $1.120{\pm}0.236$ and $FA_{mean}$ values were $0.032{\pm}0.142$ with a negative correlation (Y=1.44-1.12X). Therefore, If we understand the shape of time to signal intensity graph and the relationship between ADC and FA, It will be a criterion for distinguishing malignant diseases in breast cancer.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.986-989
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• 1999

An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.