• Progress in Medical Physics
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• v.30 no.1
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• pp.22-31
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• 2019

Purpose: To develop a new diffusion-based functional MRI (fMRI) sequence to generate apparent diffusion coefficient (ADC) maps in single excitation and evaluate the contribution of b0 signal on neuronal changes. Materials and Methods: A diffusion-based fMRI sequence was designed with single measurement that can acquire images of three directions at a time, obtaining $b=0s/mm^2$ during the first baseline condition (b0_b), followed by 107 diffusion-weighted imaging (DWI) with $b=600s/mm^2$ during the baseline and visual stimulation conditions, and another $b=0s/mm^2$ during the last activation condition (b0_a). ADC was mapped in three different ways: 1) using b0_b (ADC_b) for all time points, 2) using b0_a (ADC_a) for all time points, and 3) using b0_b and b0_a (ADC_ba) for baseline and stimulation scans, respectively. The fMRI studies were conducted on the brains of 16 young healthy volunteers using visual stimulations in a 3T MRI system. In addition, the blood oxygen level dependent (BOLD) fMRI was also acquired to compare it with diffusion-based fMRI. A sample t-test was used to investigate the voxel-wise average between the subjects. Results: The BOLD data consisted of only activated voxels. However, ADC_ba data was observed in both deactivated and activated voxels. There were no statistically significant activated or deactivated voxels for DWI, ADC_b, and ADC_a. Conclusions: With the new sequence, neuronal activations can be mapped with visual stimulation as compared to the baseline condition in several areas in the brain. We showed that ADC should be mapped using both DWI and b0 images acquired with the same conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Investigative Magnetic Resonance Imaging
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• v.18 no.1
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• pp.25-33
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• 2014

Purpose : To investigate whether quantitative parameters derived from Diffusion-weighted magnetic resonance imaging (DW-MRI) correlate with those of Dynamic contrast-enhanced MRI (DCE-MRI). Materials and Methods: Thirteen patients with pathologically or clinically proven bony metastasis who had undergone MRI prior to treatment were included. The voxel size was $1.367{\times}1.367{\times}5mm$. A dominant tumor was selected and the apparent diffusion coefficient (ADC) value and DCE-MRI parameters were obtained by matching voxels. DCE-MRI data were analyzed yielding estimates of $K^{trans}$ (volume transfer constant) and $v_e$. (extravascular extracellular volume fraction). Statistical analysis of ADC, $K^{trans}$, and $v_e$ value was conducted using Pearson correlation analyses. Results: Fifteen lesions in pelvic bones were evaluated. Of these, 11 showed a statistically significant correlation (P<0.05) between ADC and $K^{trans}$. The ADC and $K^{trans}$ were inversely related in 7 lesions and positively related in 4 lesions. This did not depend on the primary cancer or site of metastasis. The ADC and $v_e$ of 9 lesions correlated significantly. Of these, 4 lesions were inversely related and 5 lesions were positively related. Conclusion: Unlike our theoretic hypothesis, there was no consistent correlation between ADC values and $K^{trans}$ or between ADC values and $v_e$ in metastatic bone tumors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.280-285
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• 2004

In this paper, a 9-bit analog-to-digital converter (ADC) is designed for optical disk drive (ODD) servo applications. In the ADC, the circuit technique to increase the operating range of the sample-and-hold amplifier is proposed, which can process the wide-varying input common-mode range. The algorithmic ADC structure is chosen so that the area can be significantly reduced, which is suitable for SoC integration. The ADC is fabricated in a 0.18-$\mu\textrm{m} $ CMOS 1P5M technology. Measurement results of the ADC show that SNDR is 51.5dB for the sampling rate of 6.5MS/s. The power dissipation is 36.3mW for a single supply voltage of 3.3V.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.59-63
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• 2015

This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in $0.13{\mu}m$ CMOS technology. The chip area was $760{\times}280{\mu}m^2$.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.691-694
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• 1998

This paper describes a 6-b 400 MSPS CMOS folding and interpolating(F&I) ADC. To overcome the delay difference of an MSB part and an LSB part in a typical F&I ADC the ADC is composed of only one LSB part and to alleviate the offset voltage of comparators in the LSB part preamplifiers are used in front of the comparators. This paper analyzes a folder and presents a design procedure of the folder. The ADC has the DNL of 0.3 LSB and the INL of 0.6 LSB and consumes the power of 120mW $$ 3 V. The ADC is designed in a 0.6 $\mu\textrm{m}$ CMOS process.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.