Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC |
Do, Sung-Han
(Sungkyunkwan University)
Oh, Seong-Jin (Sungkyunkwan University) Seo, Dong-Hyeon (Sungkyunkwan University) Lee, Juri (Sungkyunkwan University) Lee, Kang-Yoon (Sungkyunkwan University) |
1 | Ba Ro Saim Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, and Seung-Tak Ryu "A Time-Interleaved Flash-SAR Architecture for High Speed A/D Conversion." ISCAS 2009 |
2 | Ba Ro Saim Sung, Chang-Kyo Lee, Wan Kim, Jong-In Kim, Hyeok-Ki Hong, Ghil-geun Oh, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu "A 6 bit 2 GS/s Flash-Assisted Time-Interleaved (FATI) SAR ADC with Background Offset Calibration." ASSCC 2013 |
3 | Lu Sun, Yuxiao Lu and Tingting Mo "A 300MHz 10b Time-Interleaved Pipelined-SAR ADC.", CARFIC 2013 |
4 | Binhee Kim, Long Yan, Jerald Yoo, Namjun Cho, and Hoi-Jun Yoo "An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC." ISCAS 2009 |
5 | Song Lan, Chao Yuan, Yvonne Y.H.Lam and Liter Siek "An Ultra Low-Power Rail-to-Rail Comparator for ADC Designs.", MWSCAS 2011 |
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