• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3162-3164
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• 1999

In this paper, a temperature compensating system(TCS) for LPG dispenser has been developed. A TCS includes a processor(80C196) with an AID converter. I/O port(82C55) and 6-digit vacuum fluorescent display. Based on encoding signals from the gas flow meter, different calibration values from each apparatus and temperature compensating values from the temperature sensor, the TCS controls the LPG dispensing quantity with switching on or off the solenoid valves. The temperature compensation is performed with analog-to-digital conversion of the temperature sensor. The resolution of temperature compensation is nearly $0.5^{\circ}C$ using 10-bit ADC. The field test of the TCS shows the exact temperature compensation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.74-81
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• 2007

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 1GSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. further, a novel layout technique is introduced for compact area. With the clock speed of 1GSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 500MHz, while consuming only 60mW of power. The measured INL and DNL were within $\pm$0.5 LSB, $\pm$0.7 LSB, respectively. The measured SNR was 34.1dB, when the Fin=100MHz at Fs=300MHz. The active chip occupies an area of 0.27$mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Korean Journal of Food Science and Technology
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• v.19 no.2
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• pp.129-133
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• 1987

To develop a microcomputer-based data acquisition system for measurement of variables such as temperature and weight in food process, a low-cost data acquisition system was developed using an Apple II microcomputer. The system consisted of a microcomputer, a temperature sensor made of pt-100, a strain gauge load cell for weighing, a preamplifier for signal conditionings and an interface device. Interface device was built with programmable interface chip MC 6821, tristate buffer 74244 and analog-to-digital converter ADC 0809. The analog signals of temperature and weight were serially acquisited upon the program. The BASIC language was used for operating the data acquisition and data handling programs. The system successfully measured the variables such as temperature and weight with various sampling intervals in food dehydration process.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.138-147
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• 2005

This paper presents a SPMSM(Surface-mounted Permanent Magnet Synchronous Motor) servo drive system using high performance TMS320F2812 DSP for the industrial application. The DSP(Digital Signal Processor) Controller enables an enhanced real time algorithm and cost-effective design intelligent for only exclusively motor drives which can be yield enhanced operation, fewer system components, lower control system cost, increased efficiency and high performance. The suggested system contain speed and current sensing circuits, SVPWM(Space Vector Pulse Width Modulation) and I/O interface circuit. The developed servo drive control system showns a good response characteristics results and high performance features in general purposed 400[w] machine. This system can achieve cost reduction and size minimization of controllers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• ETRI Journal
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• v.32 no.2
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• Journal of Advanced Navigation Technology
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• v.23 no.2
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• pp.97-103
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• 2019

In this paper, we designed and fabricated a receiving modem that can be applied to guided weapons can change real-time targets with little effect of fading. The designed modem consists of synchronous detector, timing error estimator, timing recovery, differential decoder and viterbi decoder, and it's implemented in FPGA so that it can be redesigned and modified according to requirements. The modem board was directly converted from IF frequency to baseband and converted into digital data through ADC. It is confirmed that it is applicable to the guided weapons that changing real-time targets through simulations, measurements and test.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.78-84
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• 2012

In this paper, we introduced the design technique about a Ka band receive module for millimeter wave seekers. The receiver module consists of a waveguide, circulator and transition for antenna connection, and a limiter and gain control amplifier for receiver protection. This module is comprised of a sum, azimuth and elevation channel for receiving monopules signal, and a SLB channel for the acquisition of jamming signal. In this paper, receiver gain and range of gain control dependent on ADC nonlinear characteristic was analyzed and designed for wide dynamic range receive. In the test result of the fabricated Ka-band receive, the frequency band is 1 GHz, the noise figure is as low as 8.2 dB, the gain is $56{\pm}2dB$, the dynamic range is 135 dB, the gain congtrol is more than 86 dB, the channel isolation is more than 35 dB.