• Journal of the Korea Institute of Information and Communication Engineering
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• 제11권9호
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제29권3호
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제28권11C호
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• pp.1152-1160
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• 2003

Start The current paper proposes an improved HD(High Definition) monitor that can support a signal input with various resolutions. Due to the inadequate performance of the built-in digital PLL(Phase-locked Loop) of an ADC(Analog to Digital Converter) and poor tolerance of ADC ICs, there are problems in the stable processing of synchronization signals with various input signals. Accordingly, the proposed synchronization signal optimization technique regenerates the horizontal synchronization signal in the vertical blanking interval based on the regularity of the synchronization signal, i.e. the timing of the falling edge signal remains constant, thereby solving the above problem and minimizing the interference of the system. As a result, the proposed system can stabilize various synchronization signals with different resolution modes.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제5권1호
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• pp.60-64
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• 2004

In this paper, we implemented a real-time remote home monitoring system which we have ported the Linux OS and HTTP(Hypertext Transfer Protocol) web server. The GoAhead web server was ported using by ARM cross compiler. And then we used the analog to digital converter ADC0809 for sensing the vii able input signal at widely separated home. We have implemented linux device driver for ADC(Analog to Digital Convertor) and CGI-C(Common Gateway Interface - C language) application program using Client pull method for monitoring real-time changing data. The factor of monitoring is temperature, intensity of illumination and gas's existence. And this system has ability which check the status of out door and gas valve. We have designed the embedded web server system for home emergency monitoring in low cost.

• The Transactions of the Korean Institute of Electrical Engineers D
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• 제54권3호
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• pp.186-190
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• 2005

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2021년도 춘계학술대회
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• pp.605-606
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• 2021

In this paper, one channel oscilloscope was implemented using arduino uno board and 1.8 inch TFT LCD. The oscilloscope is designed using the built-in analog to digital converter(ADC) inside arduino uno board as data acquisition unit and can handle up to about 1 KHz signal.

• Journal of IKEEE
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• 제23권1호
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• pp.35-43
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• 2019

A capacitor self-calibration is proposed to improve the linearity of the capacitor digital-to-analog converter (CDAC) for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with 10-bit resolution. The proposed capacitor self-calibration is performed so that the value of each capacitor of the upper 5 bits of the 10-bit CDAC is equal to the sum of the values of the lower capacitors. According to the behavioral simulation results, the proposed capacitor self-calibration improves the performances of differential nonlinearity (DNL) and integral nonlinearity (INL) from -0.810/+0.194 LSBs and -0.832/+0.832 LSBs to -0.235/+0.178 LSBs and -0.227/+0.227 LSBs, respectively, when the maximum capacitor mismatch of the CDAC is 4%. The proposed 10-bit 20-MS/s asynchronous SAR ADC is implemented using a 110-nm CMOS process with supply of 1.2 V. The area and power consumption of the proposed asynchronous SAR ADC are $0.205mm^2$ and 1.25 mW, respectively. The proposed asynchronous SAR ADC with the capacitor calibration has a effective number of bits (ENOBs) of 9.194 bits at a sampling rate of 20 MS/s about a $2.4-V_{PP}$ differential analog input with a frequency of 96.13 kHz.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• 제16권6호
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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• pp.47-50
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• 2002

An extended-counting analog to digital converter (ADC) is designed to have a high resolution(14bit) with low power consumption and small dia area. First order sigma-delta modulator with a simple counter for incremental operation eliminates the need of big decimation filter in conventional sigma-delta type ADC. To improve the accuracy and linearity, extended mode of successive approximation is followed. For 14-bit conversion operation, total 263 clocks(1 clock for reset, 256 clocks for incremental operation and extended 6 clocks for successive approximation operation) are needed with the sampling rate of 10 Ms/s This ADC is implemented in a 0.6um standard CMOS technology with a die area of 1 mm ${\times}$ 0.75 mm.