• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.378-385
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• 2008

This paper has been designed with CMOS Analog-to-Digital Converter(ADC) to use a high speed embedded system. It used flash ADC with a voltage estimator and comparator for background developed autozeroing. The speed of this architecture is almost similar to conventional flash ADC but the die size are lower due to reduced numbers of comparators and associated circuity. This ADC is implemented in a $0.25{\mu}m$ pure digital CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1023-1026
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• 2005

본 논문에서는 SDR(Software Defined Radio) 시스템을 위한 Digital IF(Intermediate Frequency) Up/Down 변환기를 설계하고 성능을 평가하였다. 설계한 시스템은 AD 변환부, DA 변환부 및 Up-Down conversion 기능을 수행하는 FPGA로 구성된다. AD 변환부는 Analog Device 사의 AD6645를 사용하였으며, DA 변환부는 Analog Device 사의 AD9775를 사용하였다. Up-Down conversion 기능을 수행하는 FPGA부는 샘플된 IF 입력을 혼합기와 NCO에 의해 기저대역(DC)으로 다운 시키는 역할을 하며, 14bit의 기저대역(DC) 신호를 혼합기와 NCO에 의해 IF 출력으로 올려주는 역할을 한다. 이러한 설계는 기존의 아날로그 헤테로다인 방식에 비하여 높은 유연성 및 우수한 성능 향상을 보여준다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1442-1447
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• 2004

In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of IKEEE
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• v.23 no.2
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• pp.636-641
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• 2019

A simple resistance deviation-to-time period converter is proposed for interfacing resistive half-bridge sensors. It consists of two 2nd generation current conveyors(CCIIs). The proposed converter has simpler circuit configuration than the conventional converters using operational amplifiers or operational transconductance amplifiers(OTAs). The proposed converter was simulated using CCII implemented with AD844 IC chips. The simulation results show that the converter has a conversion sensitivity of $0.01934ms/{\Omega}$ over a range of $100-500{\Omega}$ resistance deviations and a linearity error less than ${\pm}0.002%$.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.99-107
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• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.803-815
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• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.50-53
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• 2003

본 연구에서는 AD 변환기, QEP(Quadrature Encoder Pulse Circuit)등 모터 제어에 필요한 주변 소자의 디지털 제어를 통해서 AC 서보 모터의 벡터 제어를[3] 구현하고 시간 지연에 의한 노이즈를 최소화하기 위해 저 전압형 DSP인 TMP320F2812를 이용하였다. TMP320F2812는 MOS 타입으로 8 depth pipeline을 가진 Harvard bus 를 채택해서 최대 150MIPS의 고속 처리 능력을 갖고 있으며 12 비트의 AD 변환기 QEP 회로와 공간 전압 벡터 PWM을 발생시킬 수 있는 기능을 가진 모터 제어용 원칩 DSP이다 모터 제어에 필요한 주변 회로들을 내장한 DSP는 하드웨어적인 구성을 간소화시키고 이로 인한 비용 절감을 얻을 수 있다. 간단한 구조로 고속 연산을 하기 위해 TMP320F2812는 고정 소수점 연산 처리 방식[6]을 사용하게 되었다. 고정 소수점 연산 처리로 인한 오차는 각 변수에 대한 스케일링을 통해 유효 자리를 확보 하는 방법을 사용하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1895-1902
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• 2000

이 논문에서는 AD 변화기의 앞에 설치되는 샘플-앤드-홀드 회로의 비선형성을 보상하기 위해 신경 회로망 기법과 볼테라 급수 모델을 직접적으로 적용하는 기법을 제안한다. 제안하는 기법들의 성능을 비교하기 위해, 볼테라 급수 모델에 기반을 둔 전통적인 p차 역산 방식의 결과와 비교 검토한다. 비교 검토를 위해서는 모노-톤과 투-톤 신호를 사용하여 출력의 고조파 및 혼변조 레벨을 살펴보았다. p차 역산 방식이 역 시스템을 구하는 것이라면 제안하는 기법들은 최적화 기법에 바탕을 두고 있다고 할 수 있다. 결과를 보면 어떤 한 방식이 다른 방식보다 성능이 월등하다고 할 수 없는데, 그 이유는 각 방식마다 나름대로의 장단점을 갖고 있기 때문이다. 보상 방식의 선택은 신호의 통계적 성질, 신호 레벨, 비선형성의 정도 등을 고려해야 한다.