• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.15-16
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• 2012

This paper is study on a novel high efficiency step up-down converter using loss-less snubber capacitor. The proposed converter is accomplished that the turn-on operation of switches is on zero current switching (ZCS) by DCM. The converter is also applicable to a new quasi-resonant circuit to achieve high efficiency converter. The control switches using in the converter are operated with soft switching, that is, ZVS and ZCS by quasi-resonant method. The control switches are operated without increasing their voltage and current stresses by the soft switching technology. The result is that the switching loss is very low and the efficiency of the converter is high.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 추계학술대회
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• pp.173-174
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• 2010

In this paper, authors propose a new buck-boost converter of discontinuous conduction mode (DCM) added electric isolation. The proposed converter with DCM eliminates the complicated circuit control requirement and reduces the size of components. The general converters of high efficiency are made that the power loss of the used switching devices is minimized. To achieve the soft switching operation of the used control switches, the proposed converter uses a lossless snubber capacitor. The proposed converter achieves the soft-switching for all switching devices without increasing their voltage and current stresses. The result is that the switching loss is very low and the efficiency of converter is high. The soft switching operation of the proposed converter is verified by digital simulation and experimental results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• 전기전자학회논문지
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• 제14권2호
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• pp.90-97
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• 2010

본 논문에서는 DT-CMOS(Dynamic Threshold voltage CMOS) 스위칭 소자와 DTMOS Error Amplifier를 사용한 고 효율 전원 제어 장치(PMIC)를 제안하였다. 높은 출력 전류에서 고 전력 효율을 얻기 위하여 PWM(Pulse Width Modulation) 제어 방식을 사용하여 PMIC를 구현하였으며, 낮은 온 저항을 갖는 DT-CMOS를 설계하여 도통 손실을 감소시켰다. 벅 컨버터(Buck converter) 제어 회로는 PWM 제어회로로 되어 있으며, 삼각파 발생기, 밴드갭 기준 전압 회로, DT-CMOS 오차 증폭기, 비교기가 하나의 블록으로 구성되어 있다. 제안된 DT-CMOS 오차증폭기는 72dB DC gain과 83.5위상 여유를 갖도록 설계하였다. DTMOS를 사용한 오차증폭기는 CMOS를 사용한 오차증폭기 보다 약 30%정도 파워 소비 감소를 보였다. Voltage-mode PWM 제어 회로와 낮은 온 저항을 스위칭 소자로 사용하여 구현한 DC-DC converter는 100mA 출력 전류에서 95%의 효율을 구현하였으며, 1mA이하의 대기모드에서도 높은 효율을 구현하기 위하여 LDO를 설계하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.533-536
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• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2210-2212
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• 1997

A sensorless input current controller for three phase PWM converter is proposed. A merit of this controller is that sinusoidal input line current, unity power factor, and ripple-free DC voltage can be achieved with low-cost. The paper describes the proposed control strategy and its implementation. Simulation result for the proposed controller is compared with that of the sensor based version.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1351-1353
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• 2000

In this paper, it is proposed to constant power control of solar power system. The solar power system has disadvantage that low power density and variable power output. Proposed strategy is controled by DC/DC converter using phase shift PWM and I-PD type control applying type 1 digital system. The validity of proposed control strategy is verified from simulations results using PSIM.

• 전기학회논문지
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• 제59권2호
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• 대한전자공학회논문지
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• 제27권11호
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• pp.126-134
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• 1990

CMOS VLSI 기술에서 고속으로 데이타를 인식하기 위해서는 비교적 낮은 전달 콘덕턴스와 MOS 소자 장치들의 불균형을 극복하는 것이 중요하다. 그러나 CMOS 소자들의 한계 때문에 VLSI 회로설계는 일반적으로 CMOS 동작에 알맞도록 바이폴라 A/D(analog-to-digital)변환기가 사용되었다. 또한 파이프라인으로 종속 연결된 RSA에 의하여 전압 비교가 이뤄지는 VLSI CMOS 비교기를 설계하였다. 따라서 본 논문에서는 파이프라인으로 연결된 CMOS 비교기와 병합한 A/D 변환기를 설계하였다.

• 한국컴퓨터정보학회논문지
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• 제23권12호
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• pp.179-184
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• 2018

In this paper, we have proposed the development of DC-DC converter for LRT power supply. First of all, we have studied converter technology, main functions and characteristics were determined. In also, the converter design was carried out to meet the system design conditions. Based on this design, converter simulation is performed to enable stable charging and discharging of the vehicle system. We have performed the Light-load test according to charge mode, discharge mode. As a result, the manufactured converter performance was verified through the load test, and it's stability was confirmed.