• 전기의세계
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• v.13 no.1
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• pp.20-23
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• 1964

본 변환기는 교번자계의 원리에 의한 보통 변환기가 아니고 회전자계의 원리를 이용한 변환기로서 상변환, 주파수변화, A.C.에서 D.C. 전원변환, D.C.에서 A.C. 전원변환, 속도제어, 진상기 등을 얻을 수 있는 경제적이고 능률적인 변환기를 얻을 수 있다. 임의의 다상을 얻을 수 있는 이 변환기는 다상 전원을 필요로 하는 수은정류기 등에 응용할 수 있고 A.C.전원에서 D.C.전원의 대용량전원을 얻어 D.C.전원이 필요로 하는 직류전철의 전원, 직류송전의 전원등에 이용할 수 있고, D.C.전원에서 A.C.전원을 얻어 교류전력기를 운전할 수 있으며 D.C.송전선에서 A.C.로 변환하여 종전의 A.C.배전선에 공급하면 D.C.송전을 이용한 송전손실을 경감시킬수 있고 주파수를 변환하여 속도제어를 하는 등 광범위하게 그 응용이 가능한 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.12
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• pp.986-991
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• 2018

In this paper, an A/D conversion module was designed and fabricated to improve the dynamic range of wideband digital receivers. The A/D conversion module for expanding the dynamic range converts signals into a digital signal by branching the input signal into the normal path and the amplification path according to the input signal level. Test results of the fabricated module show that the normal path of the A/D conversion module converts an input level of -57 dBm to -12 dBm into a digital signal, and the amplification path converts an input level of -30 dBm to +12 dBm into a digital signal without distortion. This translates to an input dynamic range characteristic of 69 dB. Moreover, it is confirmed that the constant output characteristic is exhibited at an instantaneous bandwidth of 100 MHz.

• Proceedings of the Korean Society of Computer Information Conference
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• 2015.01a
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• pp.205-208
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• 2015

3D 입체영상을 제작하기 위해서는 2D 영상제작에 비해 오랜 제작 기간과 많은 비용이 발생한다. 비용 절감을 위해 기존의 2D 영상을 3D 입체영상으로 변환하는 연구가 진행되고 있다. 2D 영상을 3D 입체영상으로 변환하는 방식은 자동변환방법과 수동변환방법으로 구분할 수 있으며, 고품질의 2D-3D 변환 영상을 획득하기 위해서는 깊이정보 지도(Depth map chart)를 활용한 수동변환 방법을 많이 사용되고 있다. 하지만 2D-3D 수동변환에 사용되는 깊이정보 지도의 정량적 분석 데이터가 부족하여 사용자가 변환한 이미지에 대한 정확한 기준 깊이값 설정이 어려운 단점이 있다. 본 논문에서는 깊이정보 지도의 깊이값 정보에 대한 정량적 분석 데이터를 바탕으로 한 2D-3D 수동변환 변화범위를 제시함으로써 적정한 영상 변화를 유도할 수 있도록 한다.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.19-26
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• 2006

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them compared to the conventional ones. A moebius-band averaging technique is adopted at the proposed ADC to improve performance. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The INL and DNL are within ${\pm}0.5 LSB$, respectively. The active chip occupies an area of $0.28mm^2$ in 0.18um CMOS technology.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of Information Technology and Architecture
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• v.11 no.4
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• pp.495-504
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• 2014

This paper present a strategy of intellectual property acquisition and core technology development direction using analysis of 2D to 3D video conversion technology patent data. As a result of analysis of trends in patent 2D to 3D technology, it is very promising technology field. Using a strategic patent map using research of patent trend, you will keep ahead of the competition in 2D3D image data conversion market.