• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.5
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• pp.215-219
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• 2014

In holographic data storage (HDS), a high transmission rate is accomplished through the use of a charge coupled device array for reading two-dimensional (2D) pixel image data. Although HDS has many advantages in terms of storage capacity and data transmission rates, it also features problems, such as 2D intersymbol interference (ISI) by neighboring pixels and interpage interference (IPI) by multiple images stored in the same holographic volume. Modulation codes can be used to remove these problems. We introduce a 2D 8/9 error-correcting modulation code. The proposed modulation code exploits the trellis-coded modulation scheme, and the code rate is larger (about 0.889) than that of the conventional 6/8 balanced modulation code (an increase of approximately 13.9%). The performance of the bit error rate (BER) with the proposed scheme was improved compared with that of the 6/8 balanced modulation code and the simple 8/9 code without the trellis scheme.

• The Journal of the Korea Contents Association
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• v.9 no.7
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• pp.57-66
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• 2009

Zigbee is a universal communication standard used in USN and is utilized in various applications. Zigbee protocol provides an address within a single PAN network, and at this time, it uses DAA. This is a method that divides a 16-bit address area into blocks with a fixed size according to the depth to assign one to each node. However, this method is limited because it has to assign addresses in 16 bits. As the depth increases, the number of nodes also increases exponentially to the maximal number of routers provided to each depth. Therefore, it is difficult to construct a huge network with numerous routers and large depth as in the places which are wide or have many shadow areas. Besides, since all the operations are performed in a single PAN network, it is hard to make several PANs into a single network. This article suggests new addressing and routing methods that can construct several PAN networks into a single network and combine broad area with less limitation in the number of routers and depth by extending the Zigbee-based network. Moreover, this paper has tested its performance and has verified its usability through substantive tests.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5B
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• pp.797-808
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• 2000

This paper presents the bit error rate(BER) upper bounds for trellis coded asymmetric 8PSK(TC-A8PSK) system using the Ka-band satellite in the rain fading environment. The probability density function(PDF) for the rain fading random variable can be theoretically derived by assuming that the rain attenuation can be approximated to a long-normal distribution and the rain fading parameters are calculated by using the rain precipitation data from the Crane global model. Furthermore, we analyze the BER upper bounds of TC-A8PSK system according to the number of states in the trellis diagram and the availability of channel state information(CSI). In the past, Divsalar and Simon[9] has analyzed the BER upper bounds of 2-state TCM system in Rician fading channels however this paper is the first to analyze the BER upper bounds of TCM system in the rain fading channels. Finally, we summarize the dominant six factors which are closely related to the BER upper bounds of TC-A8PSK satellite system in the rain fading channel as follows: 1) frequency band, 2) rain intensity, 3) elevation angle, 4) signal to noise ratio, 5) asymmetric angle, and 6) availability of CSI.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.9
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• pp.2041-2047
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1947-1954
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• 2012

The first frame is encoded in intra mode which generates a larger number of bits. In addition, the first frame is used for the inter mode encoding of the following frames. Thus the initial QP for the first frame affects the first frame as well as the following frames. Traditionally, the initial QP is determined among four constant values only depending on the bpp. In the case of low bit rate video coding, the initial QP value is fixed to 40 regardless of the output bandwidth. Although this initialization scheme is simple, yet it is not accurate enough. An accurate initial QP prediction scheme should not only depends on bpp but also on the complexity of the video sequence and the output bandwidth. In the proposed scheme, we determine the initial QP according to the ratio of the first frame to the total bits allocated to a GOP. To estimate the QP of the allocated bits, Rate-QP model is used. It is shown by experimental results that the new algorithm can predict the optimal initial QP more accurately and generate the PSNR performance better than that of the existing JVT algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.1957-1964
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• 2010

In Video coding, the first frame is encoded in intra mode which generates a larger number of bits. In addition, the first frame is used for the inter mode encoding of the following frames. Thus the intial QP for the first frame of GOP affects the first frame as well as the following frames. Traditionally, the initial QP of a GOP is determined by the initial QP of the previous GOP and the average QP of the inter mode frames. In case of JM, the initial QP of a GOP is adjusted as the initial QP being less than the average QP of inter mode frames by two. However, this method is not suitable for the low bit rate video coding. In this paper, the linear relationship between the optimal QP and the ratio of the PSNR of the first frame and the average PSNR of the inter mode frames is first investigated and the linear model is proposed based on the results of the investigation. The proposed model calculate the optimal initial QP using the encoding results of the previous GOP. It is shown by experimental results that the new algorithm can predict the optimal initial QP more accurately and generate the PSNR performance better than that of the existing JM algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).