Browse > Article
http://dx.doi.org/10.17661/jkiiect.2016.9.4.419

Design of a 64b Multi-Time Programmable Memory IP for PMICs  

Cui, Dayong (Department of Electronic Engineering, Changwon National University)
Jin, Rijin (Department of Electronic Engineering, Changwon National University)
Ha, Pang-Bong (Department of Electronic Engineering, Changwon National University)
Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.9, no.4, 2016 , pp. 419-427 More about this Journal
Abstract
In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.
Keywords
MTP Cell; PMIC; Multi-Time Programmable; Small-area; Single-poly EEPROM;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 Hwang-Soo Chun, "Market Outlook and Domestic and Global Development Trend for Power Semiconductor," IITA Weekly Technology Trends, June 2009.
2 Yining Yu et al., "Design of 256 bit Single-Poly MTP Memory Based on BCD Process," J. Cent. South Univ. Technol., vol. 19, no. 12, pp. 3460-3467, Dec. 2012.   DOI
3 Yining Yu et al., "Design of 256 bit Single-Poly MTP Memory Based on BCD Process," J. Cent. South Univ. Technol., vol. 19, no. 12, pp. 3460-3467, Dec. 2012.   DOI
4 F. Torricelli et al., "Half-MOS Based Single-Poly EEPROM Cell with Program and Erase Bit Granularity," IEEE Electron Device Letters, vol. 34, no. 12, Dec. 2013.
5 Roizin, Yakov, et al., "High Density MTP Logic NVM for Power Management Applications," IEEE International Memory Workshop 2009, pp. 1-2, 2009.
6 Yoon-Kyu Kim et al.," Design of Multi-Time- Programmable Memory for PMICs," ETRI Journal, pp. 1188-1198, Dec. 2015.