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http://dx.doi.org/10.6109/jkiice.2013.17.9.2041

A Study on High Speed LDPC Decoder Algorithm based on dc saperation  

Kwon, Hae-Chan (Department of Radio Science Engineering, Korea Maritime University)
Kim, Tae-Hoon (Department of Radio Science Engineering, Korea Maritime University)
Jung, Ji-Won (Department of Radio Science Engineering, Korea Maritime University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.17, no.9, 2013 , pp. 2041-2047 More about this Journal
Abstract
In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.
Keywords
DVB-S2; Horizontal Shuffle Scheduling(HSS); row weight; Check Node Update(CNU);
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