• Korean Journal of Fisheries and Aquatic Sciences
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• v.10 no.4
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• pp.237-241
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• 1977

Optical properties were studied in the Northwest Pacific near Kamchatka Peninsula based on ten oceanographic stations from September 20 to 24, 1976. Submarine light intensity was measured by usins a submarine illuminometer (RIGO, Type: 2501-A) ; equipped with a red filter (RIGO, Type: V-R-60, wave length: 600-620 nm). Light intensity in the upper 40 m depth layer was measured at 1 m depth intervals. The absorption coefficient for red color in the area ranged from 0. 178 to 0.376 (mean 0.278) : the Secchidisc depth in the area ranged from 9 to 12 meters (mean 10.6 meters). The relationship between absorption coefficient (m) and transparency depth (D) was m=5.347/D. The rates of light penetration for red color at three different depths are computed with reference to the surface light intensity. The mean rates of light penetration were $16.36\%\;(6.45\~23.5\%),\;3.65\%\;(1.38\~7.31\%)\;and\;0.276\%(0.048\~0.647\%) $ at the depths of s m, 10 m, and 20 m, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.814-821
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• 2012

We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

• Korean Journal of Optics and Photonics
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• v.12 no.3
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• pp.190-199
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• 2001

In this paper, we have researched the depth of focus (DOF) and cutoff intensity of the $0.1{\mu}m$rule dense line'||'&'||'space pattern according to the various off-axis illumination (OAl) conditions in the optical system of 0.65 NA using ArF excimer laser (193 nm). We have also studied the variation of the DOF and cutoff intensity according to the sub-resolution pattern (hammer head type) size for optical proximity correction (OPC) applied to the capacitor pattern and the various OAl conditions in the same optical system. As a result, it is revealed that the cross type quadrupole or annular illumination is preferred to the conventional X type quadrupole for printing the $0.1{\mu}m$ rule dense pattern. Also, we can investigate the optimal illumination condition and the size of ope sub-resolution pattern to keep a consistent DGF and cutoff intensity trends.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.184-189
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• 2002

The electrical and optical properties of $(Pb_{0.91}La_{0.09})(Zr_{0.65}Ti_{0.35})O_3$(PLZT) thin films by MOCVD using ultrasonic spraying were investigated. To compensate the Pb loss by evaporation, 5 and 10 wt% of excess Pb was added to 0.2 M precursor. After deposition of films on ITO-coated glasses in oxygen atmosphere for 30 min, films were heated by in-situ RTA (rapid thermal annealing) method. When the films were heat treated at $600^{\circ}C$, perovskite single phase was obtained. The optical property of the film with 10 wt% excess Pb was excellent showing about 84 % of transmittance near 520 nm. The dielectric constant of the film was about 308 and the leakage current of the film was lower than the Pb excess 0, 5 wt% PLZT thin films.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.140-142
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• 2011

In this paper, special purpose arithmetic unit for mobile graphics accelerator is designed. The designed processor supports six operations, such as $1/{\chi}$, $\frac{1}{{\sqrt{x}}$, $log_2x$, $2^x$, $sin(x)$, $cos(x)$. The processor adopts 2nd-order polynomial minimax approximation scheme based on IEEE floating point data format to satisfy accuracy conditions and has 5-stage pipeline structure to meet high operational rates. The SFAU processor consists of 23,000 gates and its estimated operating frequency is about 400 Mhz at operating condition of 65nm CMOS technology. Because the processor can execute all operations with 5-stage pipeline scheme, it has about 400 MOPS(million operations per second) execution rate. Thus, it can be applicable to the 3D mobile graphics processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.767-773
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• 2017

In this paper, we propose a design of Intra prediction angular mode decision for HEVC encoder. Intra prediction coding of HEVC is a method for predicting a current block by referring to samples reconstructed around a current block. Intra prediction supports a total of 35 modes with 1 DC mode, 1 Planar mode, and 33 Angular modes. Intra prediction coding of HEVC works by performing all 35 modes for efficient encoding. However, in order to process all of the 35 modes, the computational complexity and operational time required are high. Therefore, this paper proposes comparing the difference in the value of the original pixel, using an algorithm that determines angular mode efficiently. This new algorithm reduces the Hardware size. The hardware which is proposed was designed using Verilog HDL and was implemented in 65nm technology. Its gate count is 14.9K and operating speed is 2GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.774-780
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• 2017

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.