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http://dx.doi.org/10.6109/jkiice.2017.21.3.585

Low-power Hardware Design of Deblocking Filter in HEVC In-loop Filter for Mobile System  

Park, Seungyong (Department of Information and Communication Engineering, Hanbat National University)
Ryoo, Kwangki (Department of Information and Communication Engineering, Hanbat National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.21, no.3, 2017 , pp. 585-593 More about this Journal
Abstract
In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.
Keywords
HEVC; In-loop Filter; Deblocking Filter; Low-power Hardware Design;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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