• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.794-796
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• 2000

This paper analyzes the method of cascading 74LS163 4-Bit Binary Counters. The 74LS163 4-Bit Binary Counter has synchronous LD. CLR functions and especially ENT, ENP, RCO to cascade some chips in order to count more 4bit binary number. The maximum operating frequency may vary according to the method of cascading. The Data sheet from Texas Instruments introduces two methods, The Ripple Carry Mode Circuit and The Carry Look Ahead Circuit, and shows that The Carry Look Ahead Circuit is more efficient than the other. However, there are only little information for user to understand and apply this to other circuits. Thus, we not only analyzed the two methods but also compared with each other in the point of performance.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10b
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• pp.281-283
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• 2000

본 논문은 EBCOT 알고리즘의 소개와 개선 방법을 제안한다. EBCOT 알고리즘은 웨이블릿 변환과 블록기반 bit-plane 부호화 방법을 활용한 알고리즘이다. EBCOT에서 사용하는 bit-plane 부호화 방법을 블록기반 fractional bit-plane 방법이라고 한다. 이 방법은 bit-plane 전체를 한번에 부호화하는 것이 아니라 블록으로 나누어 부호화를 수행하고 또한 하나의 bit-plane에 대하여서도 4번의 pass를 거치면서 bit의 context에 따라서 부호화를 수행한다. EBCOT는 웨이블릿 변환에 의하여 resolution 스케일러빌리티를 지원하고 fractional bit-plane 부호화에 의하여 SNR 스케일러빌리티를 지원하며 블록기반 부호화에 의하여 ROI에 대한 random 접근 기능을 지원한다. 그리고 EBCOT는 부호화가 완료된 다음에 bit reduction 과정을 수행한다. 이러한 특징들은 이전의 EZW나 SPIHT 방법에 비하여 장점들이라고 할 수 있다. 그러나 bit-plane 부호화를 수행하는 과정에서 효율을 개선할 수 있으며 본 논문은 이에 대한 방법을 제안한다.

• International journal of advanced smart convergence
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• v.11 no.4
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.833-841
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• 1997

In this paper, the hybrid LB-TJW(Leaky Bucket-Triggered Jumping Window) algorithm for multimedia traffic control is proposed and its performance is evaluated and analyzed. Its architecture is composed of the peak bit rate controller and the average bit rate controller. Generally, the cell which violates the peak bit rate is discraded in LBalgorithm, and the average bit rate of JW or TJW algorithm is better than that of LB algorithm. However, the hybrid LB-TJW algorithm passes it though the network if the cell does not violate the peak bit rate. If the cell violates the peak bit rate, the hybrid LB-TJW algorithm passes it to the average bit rate controller which perforithm to monitor the average bit rate of input traffic. The TJW algorithm monitors the cell that violates the average bit rate. If the cell does not violate the average bit rare, the LB-TJW algorithm passes it through the network. As simulation results, the cell loss rate and the buffer size of the LB-TJW algorithm is reduced to half as much as those of LB algortihm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.958-964
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• 2007

In this paper, we derive the relationship between the bit error probability (BEP) of maximum a posteriori (MAP) bit detection and the bit minimum mean square error (MMSE), that is, the BEP is greater than a quarter of the bit USE and less than a half of the bit MMSE. By using this result, the lower and upper bounds of the derivative of the mutual information are derived from the BEP and the lower and upper bounds are easily obtained in the multiple-input multiple-output (MIMO) communication systems with the bit-linear linear-dispersion (BLLD) codes in the Gaussian channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.1-6
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• 2010

We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.533-536
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• 2004

In this paper, CMOS A/D converter with 10bit 32MSPS at 3.3V is designed for HPNA 2.0. In order to obtain the resolution of 10bit and the character of high-speed operation, we present multi-stage type architecture. That consist of sample and hold(S&H), 4bit flash ADC and 4bit Multiplier D/A Converter (MADC) also the Overflow and Underflow for timing error correct of Digital Correct ion Logic (DCL). The proposed ADC is based on 0.35um 3-poly 5-metal N-well CMOS technology. and it consumes 130mW at 3.3V power supply.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1121-1127
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• 2010

This paper describes the equivalent circuit of $45^{\circ}$ layer, one of $11.25^{\circ}$, $22.5^{\circ}$, and $45^{\circ}$ phase shift layers, which are needed for X-band Radant lens 4-bit phase shifter. The equivalent circuit is extracted by comparing the CST's MWS results with the Agilent's ADS results for $45^{\circ}$ phase shift layer. The simulated result is compared with the measured one. Using the extracted equivalent circuit, the phase bit simulation results of 4-bit Radant lens are also presented.