International journal of advanced smart convergence

The Institute of Internet, Broadcasting and Communication (한국인터넷방송통신학회)
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A Study of 0.5-bit Resolution for True-Time Delay of Phased-Array Antenna System

  • Cha, Junwoo (Dept. of Electronic Engineering, Hankuk University of Foreign Studies) ;
  • Park, Youngcheol (Dept. of Electronic Engineering, Hankuk University of Foreign Studies)
  • Received : 2022.10.13
  • Accepted : 2022.10.17
  • Published : 2022.12.31
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Abstract

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm2. In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

Keywords

Acknowledgement

This work was supported by the Research Fund of Hankuk Univ. of Foreign Studies, and by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No.2020R1F1A1073315). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.

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