• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.547-554
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• 2008

In this paper, two-stage pipelined floating-point multiplier (FP-MUL) is designed. The FP-MUL processor supports single precision multiplication for 3D graphic APIs, such as OpenGL and Direct3D and has area-efficient and low-latency architecture via saturated arithmetic, area-efficient sticky-bit generator, and flagged prefix adder. The FP-MUL has about 4-ns delay time under $0.13{\mu}m$ CMOS standard cell library and consists of about 7,500 gates. Because its maximum performance is about 250 MFLOPS, it can be applicable to mobile 3D graphics application.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.69-72
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• 2003

This paper presents a signal processing IC for digital HDTV, which is designed to operate in bunt-in HDW or in HD-set-top Box. The chip supports de-multiplexing an ISO/IEC 13818-1 MPEG-2 TS stream. It decodes MPEG-2 MP@HL video bitstream, and provides high-quality scaled video for display on HDTV monitor. The chip consists of ARM7TDMI for TS-Demux, PCI interface, Audio interface, MPEG2 MP@HL video decoder Display processor, Graphic processor, Memory controller, Audio int3face, Smart Card interface and UART. It is fabricated using Sam sung's 0.18-um and the package of 492-pin BGA is used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.20-25
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• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.3
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• pp.124-132
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• 2003

The goal of this paper is to propose a virtual instrumentation system based on three dimensional current coordinates for monitoring power quality A developed system with various experimental graphic screens and numerical results is made up 586-PC and DSP(digital signal processor) board, power quality analyzing and evaluating software for windows. Power parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis. results are visualized by 3-D current coordinates, and it Is compared and evaluated with conventional time / frequency domain. To verify the validity of the proposed system, power and harmonic parameters of single phase induction motor drives is analyzed and verified.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.305-316
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• 2006

Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.190-197
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• 2002

The goal of this paper is to propose a virtual instrumentation system based on three dimensional current coordinates for monitoring power quality. A developed system with various experimental graphic screens and numerical results is made up 586-PC and DSP(digital signal processor) board, power quality analyzing and evaluating software for windows. Power parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis results are visualized by 3-D current coordinates, and it is compared and evaluated with conventional time/frequency domain. To verify the validity of the proposed system, power and harmonic parameters of single phase induction motor drive system is analyzed and verified.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.89-96
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• 2013

The graphic processor unit (GPU) has been developed to process not only graphic data but also general system data. It shows a better performance than CPU in algorithm for 3D graphics and parallel program. In order to execute algorithm for CPU on GPU, we should understand about GPU architectures and rewrite program considering parallel processing capability and new memory model of GPU. For this reasons, a performance prediction model for the algorithm and its predicted performance through GPU system are required. These can predict problems in GPU application development or construct a performance evaluation standard for GPU. In this paper, we applied the AES encryption algorithms on our performance model and accomplished performance prediction with high accuracy under a heavy workload.

• Progress in Medical Physics
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• v.3 no.1
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• pp.71-78
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• 1992

This study describes the design of the biophysiological signal processing analyzer which can collect and analyze the biosignal raw data. System hardware is consisted of the IBM PC AT. pre-amplifier. AID converter, Counter/Timer. and RS-232C processor. Biophysiological signal data were processed by the software digital filter. FFT and graphic processing routine. The tachogram and FFT of the the peak to peak interval time was accomplished by the Graphic user interface software using the biophysiological signal processed data. Using this system. the powerspectrum of the heart rate variability during the long term could be observed. Experimental results of this system approach our purpose. which is improved the cost performance. easy to use. reducing raw-data noise and optimizing model for digital filter.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.113-121
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• 1989

A software interface called CGI-K including device driver routines and graphics primitives for the grphic board "K" was designed, implemented in the Design Automation Laboratory of KAIST and installed on IBM PC/AT, using assembly and C language supported by TMS 34010 grphics processor. Several algorithms generating the graphics primitives such as box, circle, pie chord are proposed. The drawing speed of CGI-K on the graphic board K was found out to be three to ten times faster than that of the EGA for several examples. A 2-D graphics editor called GRIM (graphics input and modification) and a 3-dimensional graphics renderer called IPCHE which can draw 3-D objects were developed as two major application programs running on CGI-K. The graphics primitives supported in GRIM include polygon, box, circle, and ace. The IPCHE receives a 3-D objects data file and displays the 3-D object on the screen with hidden surface removal, shading, and perspective scaling.