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http://dx.doi.org/10.3745/KIPSTA.2006.13A.4.305

Design of a Parallel Rendering Processor Architecture with Effective Memory System  

Park Woo-Chan (세종대학교 컴퓨터공학과)
Yoon Duk-Ki (세종대학교 컴퓨터공학과)
Kim Kyoung-Su (세종대학교 컴퓨터공학과)
Publication Information
The KIPS Transactions:PartA / v.13A, no.4, 2006 , pp. 305-316 More about this Journal
Abstract
Current rendering processors are organized mainly to process a triangle as fast as possible and recently parallel 3D rendering processors, which can process multiple triangles in parallel with multiple rasterizers, begin to appear. For high performance in processing triangles, it is desirable for each rasterizer have its own local pixel cache. However, the consistency problem may occur in accessing the data at the same address simultaneously by more than one rasterizer. In this paper, we propose a parallel rendering processor architecture resolving such consistency problem effectively. Moreover, the proposed architecture reduces the latency due to a pixel cache miss significantly. For the above two goals, effective memory organizations including a new pixel cache architecture are presented. The experimental results show that the proposed architecture achieves almost linear speedup at best case even in sixteen rasterizers.
Keywords
Computer Graphics; Rendering Processor; Parallel Rendering; Graphic Hardware;
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