• The Korean Journal of Petroleum Geology
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• v.6 no.1_2 s.7
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• pp.1-7
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• 1998

A multichannel seismic profile from the southwestern margin of the Ulleung Basin, East Sea, was analysed in detail to interpret the middle to late Miocene sequence stratigraphic evolution of the area. A regressive package is overlying a transgressive package which, in turn, is underlain by older uplifted and deformed sedimentary layers. A prominent condensed section separates the regressive and transgressive packages. The transgressive package is characterized by onlapping onto the underlying uplifted and deformed strata. The regressive package contains six prograding sequences composed of seismically resolvable lowstand, highstand, and transgressive systems tracts. Most of the depositional sequences comprise lowstand systems tracts consisting of basin-floor fan, slope fan, and prograding complex. Potential reservoirs in the regressive package are turbidite sands in basin-floor fans, channel-fill sands and overbank sand sheets in slope fans, and incised valley-fill sands in the shelf. The shallow marine sands in transgressive packages are another type of reservoir. Detailed sequence stratigraphic analysis, seismic data reprocessing, and 3-D seismic survey are suggested for the successful hydrocarbon exploration in the study area.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.63-69
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• 2013

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.5
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• Publications of The Korean Astronomical Society
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• v.30 no.2
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• pp.675-677
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• 2015

A data simulator and reduction package for the Devasthal Optical Telescope Integral Field Spectrograph (DOTIFS) has been developed. Since data reduction for the Integral Field Spectrograph (IFS) requires complicated procedures due to the complex nature of the integral spectrograph, common reduction procedures are usually not directly applicable for such an instrument. Therefore, the development of an optimized package for the DOTIFS is required. The data simulator observes artificial object and simulates CCD images for the instrument considering various effects; e.g. atmosphere, sky background, transmission, spectrograph optics aberration, and detector noise. The data reduction package has been developed based on the outcomes from the DOTIFS data simulator. The reduction package includes the entire processes for the reduction; pre-processing, flat-fielding, and sky subtraction. It generates 3D data cubes as a final product, which users can use for science directly.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.15-16
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• 2008

• Journal of Welding and Joining
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• v.29 no.3
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• pp.45-50
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• 2011

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.487-488
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• 2006

In this paper, we analyzed the FBGA packages operating in high speeds and high frequency rates for DRAM. Using 3D simulations, we could extract s-parameters of packages. We realize that the proposed FBGA package does not operate properly at 3Gbps bacause the FBGA package have delta-I noise($V_{{\Delta}I-peak}$) of 132.0mV and crosstalk of 300mV, which is 25% of the operating clock level.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.