Reliability Study of 3D TSV Package Using Solder Interconnect
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Lee, Haeng-Soo
(울산과학대학 디지털 기계학부)
Kim, Kyoung-Ho (서울과학기술대학교 NID융합기술대학원) Choa, Sung-Hoon (서울과학기술대학교 NID융합기술대학원) |
| 1 | Seungmin Hyun and Changwoo Lee : TSV Core Technology for 3D IC Packaging, Journal of KWS, 27-3 (2009), 4-9 (in Korea) 과학기술학회마을 DOI |
| 2 | Sehoon Yoo and Chang-woo Lee : Through Silicon Via Filling and Fine Pitch Joining Technology for 3D Electronic Package, Journal of KWS, 27-3 (2009), 17-22 (in Korea) 과학기술학회마을 DOI |
| 3 | M.C. Hsieh and C. K. Yu: Thermo-mechanical Simulations For 4-Layer StackedIC Packages, EuroSimE Conf., (2008) 1-7 |
| 4 | J. Zhang, Max O. Bloomfield, J. Lu, R. J. Gutmann, and T. S. Cale : Modeling Thermal Stresses in 3-D IC Interwafer Interconnects, IEEE Transactions on Semiconductor Manufacturing, 19-4 (2006) 437-448 DOI ScienceOn |
| 5 | C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan and T. C. Chai : Nonlinear thermal stress/strain analyses of copper filled TSV and their flip-chip microbumps, 2008 Electronic Components and Technology Conference, (2008) 1073-1081 |
| 6 | L. J. Ladani : Numerical analysis of thermo- mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits, Microelectronic Eng., Vol. 87, (2010) 208-215 DOI ScienceOn |
| 7 | K H. Lu, X. Zhang, S. Ryu, J. Im, R. Huang, and P. S. Ho : Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias, 2009 Electronic Components and Technology Conference, 630-634 DOI |
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