• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.24 no.1
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• pp.13-16
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• 2018

Powdered infant formula is susceptible to oxidation in the presence of oxygen. Even though the product is usually packaged in nitrogen atmosphere, the oxygen ingress through the package layer may occur in case of flexible pouches and affects the oxidation of the product. $O_2$ barrier of the package is thus important variable to protect the product from oxidative deterioration. $O_2$ barrier property was investigated for aluminum-laminated small pillow packs of $3.5{\times}17.5cm$. Storage temperature and combination of primary and secondary packages were evaluated as variables affecting the barrier for conditions of empty pouch flushed with nitrogen. Apparent oxygen transmission rate of the primary package exposed to air was $2.32{\times}10^{-3}mL\;(STP)\;atm^{-1}\;d^{-1}$ at $30^{\circ}C$ and its temperature dependence could be explained by activation energy of $28.5kJ\;mol^{-1}$ in Arrhenius relationship. The additional secondary package of nylon/PE film containing 20 primary packages was ineffective in modulating package $O_2$ transmission and was only marginally helpful when combined with oxygen scavenger. The same was true in suppressing the product oxidation when the primary package was filled with 14 g of the formula.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.837-838
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• 2013

• Journal of Welding and Joining
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• v.27 no.3
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• pp.17-22
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• 2009

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Journal of Navigation and Port Research
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• v.27 no.2
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• pp.217-221
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• 2003

In this work, we used a novel RF-CSP to develop a broadband amplifier MMIC, including all the matching and biasing components, for Ku and K band applications. By utilizing an ACF for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. STO (SrTiO$_3$) capacitors were employed to integrate the DC biasing components on the MMIC. A pre-matching technique was used for the gate input and drain output of the FETs to achieve a broadband design for the amplifier MMIC. The amplifier CSP MMIC exhibited good RF performance (Gain of 12.5$\pm$1.5 dB, return loss less than -6 dB, PldB of 18.5$\pm$1.5 dBm) over a wide frequency range. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the Ku/K band.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.201-204
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• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.

• Nuclear Engineering and Technology
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• v.30 no.5
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• pp.462-469
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• 1998

A package to transport high-level radioactive materials is required to withstand normal transport and hypothetical accident conditions pursuant to the IAEA and domestic regulations. The package should maintain the structural safety not to release radioactive material in any condition. The structural safety of the package has been evaluated by tests using proto-type or scaled-down models, however, the method by analysis is gradually utilized due to recent advancement of computers and computer codes. In this paper, to evaluate the structural safety of a radioisotope package of the KAERI, the three dimensional impact analyses under 9m free drop and 1m puncture were performed with an explicit finite-element code, the LS-DYNA3D code. The maximum stress intensity on each part was calculated and the structural safety of the package was evaluated in accordance with the regulations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.269-276
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• 2016

This paper presents a 2.65 GHz Doherty power amplifier with internally-matched GaN HEMT. Internal matching circuits were adopted to match its harmonic impedances inside the package. Simultaneously, due to the partially matched fundamental impedance, input and output matching networks become simpler. Bond wires and parasitic elements of transistor package were predicted by EM simulation. For the LTE signal with 6.5 dB PAPR, the implemented Doherty power amplifier shows a power gain of 13.0 dB, a saturated output power of 55.4 dBm, an efficiency of 49.1 %, and ACLR of -26.3 dBc at 2.65 GHz with an operating voltage of 48 V.