• Journal of Biosystems Engineering
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• v.35 no.3
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• pp.189-196
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• 2010

This study was conducted to develop an non-contact ultrasonic transducer for measurement of fruit firmness. The center frequency of non-contact ultrasonic transducer was 500 kHz. As an active element of non-contact ultrasonic transducer, the 1-3 piezoelectric composite material was selected. That material has high piezoelectric properties such as electro-mechanical coupling factor, $k_t$ and piezoelectric voltage constant, $d_{33}$ and also that material has low acoustical impedance which enables to matching the acoustical impedances between piezoelectric material and air. As a front matching material between 1-3 piezoelectric composite material and air, various kinds of paper with different thickness were tested. To control the dead-zone of the fabricated non-contact ultrasonic transducer, the backing material composed of epoxy resin and tungsten powder were made and evaluated. The fabricated non-contact ultrasonic transducer for fruit showed that the cneter frequency, bandwidth and beamwidth were approximately 480 kHz, 30 % and 12 mm, respectively. It was concluded that non-contact measurement of apple firmness would be possible by using the fabricated non-contact ultrasonic transducer.

• Journal of Sensor Science and Technology
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• v.7 no.4
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• pp.293-299
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• 1998

An objective of this study is to develop a voltage measuring device that uses a gas-filled switch (GS) on 22.9 kV-y extra-high voltage distribution lines. The voltage measuring device proposed in this paper is a kind of capacitive divider which consists of a detecting electrode attached outside of the bushing of GS, an impedance matching circuit, and a voltage buffer. It can be easily installed in an established GS without changing the structure. For the calibration and application investigations, the voltage measuring device was set up in the 25.8 kV 400 A GS, and a step pulse generator having 5 ns rise time is used. As a result, it was found that the frequency bandwidth of the voltage measuring device ranges from 1.35 Hz to about 13 MHz. The error of voltage dividing ratio which is evaluated by the commercial frequency voltage of 60 Hz was less than 0.2%. In addition, voltage dividing ratio in the commercial frequency voltage and in a non-oscillating impulse voltage were compared, and their deviation were less than 0.7%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.52-58
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• 2009

A low voltage, low power delta-sigma modulator is proposed for cardiac pacemaker applications. A cascade of delta-sigma modulator stages that employ a feedforward topology has been used to implement a high-resolution oversampling ADC under the low supply. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption. An experimental prototype of the proposed circuit has been implemented in a $0.35-{\mu}m$ CMOS process, and it achieves 61-dB SNDR, 63-dB SNR, and 65-dB DR for a 120-Hz signal bandwidth at 7.6-kHz sampling frequency. The power consumption is only 280 nW at 1-V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.60-68
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• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• ETRI Journal
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• v.38 no.2
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• pp.235-243
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• 2016

A low-noise readout integrated circuit (ROIC) for a microelectromechanical systems (MEMS) microphone is presented in this paper. A positive feedback signal amplification technique is applied at the front-end of the ROIC to minimize the effect of the output buffer noise. A feedback scheme in the source follower prevents degradation of the noise performance caused by both the noise of the input reference current and the noise of the power supply. A voltage booster adopts noise filters to cut out the noise of the sensor bias voltage. The prototype ROIC achieves an input referred noise (A-weighted) of -114.2 dBV over an audio bandwidth of 20 Hz to 20 kHz with a $136{\mu}A$ current consumption. The chip is occupied with an active area of $0.35mm^2$ and a chip area of $0.54mm^2$.

• Proceedings of the KIEE Conference
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• 1997.07e
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• pp.1824-1826
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• 1997

In this paper, in order to obtain statistical informations on lightning electromagnetic waveforms, electric field waveforms produced by lightning return strokes were measured and analyzed. The electric field measuring system consists of hemisphere antenna 30[cm] in diameter, integrator and data acquisition. system. The frequency bandwidth of the measuring system is 200[Hz] to 1.56[MHz], and the sensitivity is 0.96[mV/V/m]. The mean value of front time of electric field waveforms produced by positive lightning return strokes is 5.87[${\mu}s$], and that of negative is 4.12[${\mu}s$]. The mean values of zero-crossing time for positive or negative electric field waveforms are 35.00 and 26.61[${\mu}s$], respectively. The mean value of percentage dip-depth for positive electric field waveforms is 33.68[%], and that for negative is 28.36[%].