• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.498-498
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• 2013

Atmospheric Pressure Plasmas have pioneered a new field of plasma for biomedical application bridging plasma physics and biology. Biological and medical applications of plasmas have attracted considerable attention due to promising applications in medicine such as electro-surgery, dentistry, skin care and sterilization of heat-sensitive medical instruments [1]. Traditional approaches using electronic devices have limits in heating, high voltage shock, and high current shock for patients. It is a great demand for plasma medical industrial acceptance that the plasma generation device should be compact, inexpensive, and safe for patients. Microwave-excited micro-plasma has the highest feasibility compared with other types of plasma sources since it has the advantages of low power, low voltage, safety from high-voltage shock, electromagnetic compatibility, and long lifetime due to the low energy of striking ions [2]. Recent experiment [2] shows three-log reduction within 180-s treatment of S. mutans with a low-power palm-size microwave power module for biomedical application. Experiments using microwave plasma are discussed. This low-power palm-size microwave power module board includes a power amplifier (PA) chip, a phase locked loop (PLL) chip, and an impedance matching network. As it has been a success, more compact-size module is needed for the portability of microwave devices and for the various medical applications of microwave plasma source. For the plasma generator, a 1.35-GHz coaxial transmission line resonator (CTLR) [3] is used. The way of reducing the size and enhancing the performances of the module is examined.

• Journal of the Optical Society of Korea
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• v.1 no.2
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• pp.110-115
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• 1997

We report effcient cascaded Raman generation and signal amplification at 1.3.mu.m achieved in a ring resonator constructed solely from fiber components, i.e. fusion WDM couplers. Low-loss single-mode fiber with moderate $GeO_2$ content (18 mole %) is used as an active medium and pumped by a Nd:YAG laser at 1.064.mu.m. In a resonant cascaded geometry, this generates the third Stokes line at 1.24.mu.m, which acts as a pump for signal wavelength around 1.3.mu.m. A DFB laser operating at 1.315.mu.m is used to provide an input signal. An output signal powers up to 20 dBm (100 mW) with a 28 dB Raman gain are attained, where the Nd:YAG pump power is 3.4 W. It is also shown experimentally that it is important to use optical filters to suppress feedback from the resonator, permitting high Raman gain and good signal quality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.89-94
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• 2008

In this paper, a cascade of a wideband amplifier and a high-Q bandpass filter (BPF) has been realized in a 0.18mm CMOS technology for the applications of subsampling direct-conversion receivers. The wideband amplifier is designed to obtain the -3dB bandwidth of 5.4GHz, and the high-Q BPF is designed to select a 2.4GHz RF signal for the Bluetooth specifications. The measured results demonstrate 18.8dB power gain at 2.34GHz with 31MHz bandwidth, corresponding to the quality factor of 75. Also, it shows the noise figure (NF) of 8.6dB, and the broadband input matching (S11) of less than -12dB within the bandwidth. The whole chip dissipates 64.8mW from a single 1.8V supply and occupies the area of $1.0{\times}1.0mm2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.358-365
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• 2008

A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.189-197
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• 2014

This work proposes a 12b 100 MS/s $0.11{\mu}m$ CMOS three-step hybrid pipeline ADC for high-speed communication and mobile display systems requiring high resolution, low power, and small size. The first stage based on time-interleaved dual-channel SAR ADCs properly handles the Nyquist-rate input without a dedicated SHA. An input sampling clock for each SAR ADC is synchronized to a reference clock to minimize a sampling-time mismatch between the channels. Only one residue amplifier is employed and shared in the proposed ADC for the first-stage SAR ADCs as well as the MDAC of back-end pipeline stages. The shared amplifier, in particular, reduces performance degradation caused by offset and gain mismatches between two channels of the SAR ADCs. Two separate reference voltages relieve a reference disturbance due to the different operating frequencies of the front-end SAR ADCs and the back-end pipeline stages. The prototype ADC in a $0.11{\mu}m$ CMOS shows the measured DNL and INL within 0.38 LSB and 1.21 LSB, respectively. The ADC occupies an active die area of $1.34mm^2$ and consumes 25.3 mW with a maximum SNDR and SFDR of 60.2 dB and 69.5 dB, respectively, at 1.1 V and 100 MS/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.70-79
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• 2016

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.