DOI QR코드

DOI QR Code

Range-Scaled 14b 30 MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors

  • Park, Jun-Sang (Department of Electronic Engineering, Sogang University) ;
  • Jeong, Jong-Min (Department of Electronic Engineering, Sogang University) ;
  • An, Tai-Ji (Department of Electronic Engineering, Sogang University) ;
  • Ahn, Gil-Cho (Department of Electronic Engineering, Sogang University) ;
  • Lee, Seung-Hoon (Department of Electronic Engineering, Sogang University)
  • Received : 2015.07.17
  • Accepted : 2015.11.01
  • Published : 2016.02.28

Abstract

This paper proposes a low-power range-scaled 14b 30 MS/s pipeline-SAR composite ADC for high-performance CIS applications. The SAR ADC is employed in the first stage to alleviate a sampling-time mismatch as observed in the conventional SHA-free architecture. A range-scaling technique processes a wide input range of 3.0VP-P without thick-gate-oxide transistors under a 1.8 V supply voltage. The first- and second-stage MDACs share a single amplifier to reduce power consumption and chip area. Moreover, two separate reference voltage drivers for the first-stage SAR ADC and the remaining pipeline stages reduce a reference voltage disturbance caused by the high-speed switching noise from the SAR ADC. The measured DNL and INL of the prototype ADC in a $0.18{\mu}m$ CMOS are within 0.88 LSB and 3.28 LSB, respectively. The ADC shows a maximum SNDR of 65.4 dB and SFDR of 78.9 dB at 30 MS/s, respectively. The ADC with an active die area of $1.43mm^2$ consumes 20.5 mW at a 1.8 V supply voltage and 30 MS/s, which corresponds to a figure-of-merit (FOM) of 0.45 pJ/conversion-step.

Keywords

References

  1. J. H. Kim et al., "A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor," in Proc. ISSCC Dig. Tech. Papers, pp. 390-392, Feb., 2012.
  2. S. H. Cho, J. S. Park, G. C. Ahn, and S. H. Lee, "A 14-10b dual-mode low-noise pipeline ADC for high-end CMOS image sensors," in Analog Integrated Circuits and Signal Processing, vol. 80, no. 3, pp. 437-447, Sept., 2014. https://doi.org/10.1007/s10470-014-0356-3
  3. H. Y. Lee, T. H Oh, H. J. Park, H. S. Lee, M. Spaeth, and J. W. Kim, "A 14-b 30MS/s$0.75mm^2$ pipelined ADC with on-chip digital selfcalibration," in Proc. CICC, pp. 313-316, Sept., 2007.
  4. Weitao Li, Cao Sun, Fule Li, and Zhihua Wang, "A 14-bit pipelined ADC with digital background nonlinearity calibration," in Proc. IEEE Int. Symp. Circuits and Syst., pp. 2448-2451, May, 2013.
  5. A. Meruva, B. Jalali-Farahani, "A 14-b 32MS/s pipelined ADC with novel fast-convergence comprehensive background calibration," in Proc. IEEE Int. Symp. Circuits and Syst., pp. 956-959, May, 2009.
  6. Y. J. Cho, K. H. Lee, H. C. Choi, S. H. Lee, K. H. Moon, and J. W. Kim, "A calibration-free 14b 70MS/s $3.3mm^2$ 235mW 0.13um CMOS pipeline ADC with high-matching 3-D symmetric capacitors," in Proc. CICC, pp. 485-488, Sept., 2006.
  7. B. G. Lee, B. M. Min, G. Manganaro, and J. W. Valvano, "A 14b 100MS/s pipelined ADC with a merged active S/H and first MDAC," in Proc. ISSCC Dig. Tech. Papers, pp. 248-611, Feb., 2008.
  8. H. Van de Vel et al., "A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS," IEEE J. Solid-State Circuits, Vol. 44, no. 4, pp. 1047-1056, Apr., 2009. https://doi.org/10.1109/JSSC.2009.2014702
  9. B. G. Lee and R. Tsang, "A 10-bit 50 MS/s pipeline ADC with capacitor-sharing and variablegm opamp," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 883-890, Mar., 2009. https://doi.org/10.1109/JSSC.2009.2013761
  10. H. C. Choi, Y. J. Kim, G. C, Ahn, and S. H. Lee, "A 1.2-V 12-b 120-MS/s SHA-free dual-channel Nyquist ADC based on midcode calibration," IEEE Trans. on Circuits and Systems I, Reg. Papers, vol. 56, no. 5, pp. 894-901, May, 2009. https://doi.org/10.1109/TCSI.2009.2015200
  11. K. J. Lee, K. J. Moon, K. S. Ma, K. H. Moon, and J. W. Kim, "A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling," in Proc. CICC, pp. 165-168, Sept., 2008.
  12. C. Myers, J. Li, D. Y. Chang, and U. K. Moon, "Low voltage high-SNR pipeline data converters," in Proc. IEEE NEWCAS, pp. 245-248, June, 2004.
  13. D. Y. Chang et al., "A 1.2V programmable ADC for a multi-mode transceiver in 0.13um CMOS," in Proc. EuMIC, pp. 151-154, Oct., 2008.
  14. D. H. Hwang et al., "A range-scaled 13b 100MS/s 0.13um CMOS SHA-free ADC based on a single reference," Journal of Semiconductor Technology and Science, vol. 13, no. 2, pp. 98-107, Apr., 2013. https://doi.org/10.5573/JSTS.2013.13.2.98
  15. K. H. Lee, S. W. Lee, Y. J. Kim, K. S. Kim, and S. H. Lee, "Ten-bit 100 MS/s 24.2 mW $0.8mm^2$ 0.18um CMOS pipeline ADC based on maximal circuit sharing schemes," Electron. Lett., vol. 45, no. 25, pp. 1296-1297, Dec., 2009. https://doi.org/10.1049/el.2009.2199
  16. B.-Y. Koo, S.-J. Park, G.-C. Ahn, and S.-H. Lee, "A Single Amplifier-Based 12-bit 100MS/s 1V 19mW $0.13{\mu}m$ CMOS ADC with Various Power and Area Minimized Circuit Techniques," IEICE Trans. Electron., vol. E94-C, no. 8, pp. 1282-1288, Aug., 2011. https://doi.org/10.1587/transele.E94.C.1282
  17. Y. J. Kim, K. H. Lee, M. H. Lee, and S. H. Lee, "A 0.31pJ/conversion-Step 12-bit 100MS/s $0.13{\mu}m$ CMOS A/D converter for 3G communication systems," IEICE Trans. Electron., vol. E92-C, no. 9, pp. 1194-1200, Sept., 2009. https://doi.org/10.1587/transele.E92.C.1194
  18. C. C. Lee, and M. P. Flynn, "A 14b 23 MS/s 48mW Resetting ${\Sigma}{\Delta}$ ADC," IEEE Trans. Circuits Syst. I, vol. 58, no. 6, pp. 1167-1177, June, 2011. https://doi.org/10.1109/TCSI.2010.2097716
  19. H. Y. Lee, B. Lee, and U. K. Moon, "A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V Two-Step Pipelined ADC in $0.13{\mu}m$ CMOS," in Proc. ISSCC Dig. Tech. Papers, pp. 474-476, Feb., 2012.
  20. K. Iizuka, H. Matsui, M. Ueda, and M. Daito, "A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS/s," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 883-890, Apr., 2006. https://doi.org/10.1109/JSSC.2006.870788